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1 8351b C C AT86RF233 features ? high performance rf - cmos 2.4ghz radio transceiver targeted for ieee ? 802.15.4, zigbee ? , rf4ce, 6lowpan, and ism applications ? industry leading link budget: - receiver sensitivity - 101 dbm - progra mmable tx output power from - 17dbm up to +4 dbm ? ultra - low current consumption: - deep_sleep = 0.02 a - trx_off = 300 a - rx_on = 11.8 ma (listen) ? smart receiving techniques enable further current reduction in listen mode between 10 to 50% from 11.8 ma ? desensitation will enable further reduction up to 1 ma - busy_tx = 13.8 ma (at max. transmit power) ? ultra - low supply voltage ( 1.8 v to 3.6 v ) with internal regulator ? support for coin cell operation ? optimized for low bom cost and ease of produc tion: - few external components necessary (crystal, capacitors and antenna) ? easy to use interface: - registers, frame buffer, and aes accessible through fast spi - only two microcontroller gpio lines necessary - one interrupt pin from radio transceiver - clock outpu t with prescaler from radio transceiver ? radio transceiver features: - 128 - byte fifo (sram) for data buffering - fully integrated, fast settling pll to support frequency hopping - supports 500 khz channel spacing - battery monitor - fast wake - up time < 0.4msec ? special ieee 802.15.4 ? - 2011 hardware support: - fcs computation and clear channel assessment - rssi measurement, energy detection and link quality indication ? mac hardware accelerator: - automated acknowledgement, csma - ca and retransmission - automatic address filtering - automated fcs check ? extended feature set hardware support: - aes 128 - bit hardware accelerator - antenna diversity and rx/tx indication - supported psdu data rates: 250kb/s, 500kb/s, 1000kb/s and 2000kb/s - true random number generation for security application - reduced power consumption modes (patent pending) ? industrial temperature range: - - 40 c to +85 c ? i/o and packages: - 32 - pin low - profile qfn package 5 x 5 x 0.9mm3 - rohs/fully green ? compliant to ieee 802.1 5.4 - 2003/2006/2011 ? compliant to en 300 328/440, fcc - cfr - 47 part 15, arib std - 66, rss - 210 low power, 2.4 ghz transceiver for zigbee, rf4ce, ieee 802.15.4, 6lowpan, and ism applications AT86RF233 preliminary rev. 8351b C mcu wireless C 06/12
2 8351b C C AT86RF233 1 pin - out diagram figure 1 - 1 . atmel AT86RF233 pin - out diagram . note: 1. the exposed paddle is electrically connected to the die inside the package. it shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability. 3 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 2 3 4 5 6 7 8 a t 8 6 r f 2 3 3 c l k m d v s s d i g 3 d i g 4 a v s s a v s s r f p r f n d v s s / r s t d i g 1 d i g 2 s l p _ t r d v s s d v d d d v d d d e v d d d v s s s c l k m i s o d v s s m o s i / s e l i r q x t a l 2 x t a l 1 a v s s e v d d a v d d a v s s a v s s a v s s 3 1 3 0 2 9 2 8 2 7 2 6 2 5 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 a v s s e x p o s e d p a d d l e
3 8351b C C AT86RF233 1.1 pin descriptions table 1 - 1 . atmel AT86RF233 pin description . pins name type description 1 dig3 digital output (ground) 1. rx/tx indicator, see section 11.5 2. if disabled, pull - down enabled (avss) 2 dig4 digital output (ground) 1. rx/tx indicator (dig3 inverted), see section 11.5 2. if disabled, pull - down enabled (avss) 3 avss ground ground for rf signals 4 rfp rf i/o differential rf signal 5 rfn rf i/o differential rf signal 6 avss ground ground for rf signals 7 dvss ground digital ground 8 / rst digital input chip r eset ; active low 9 dig1 digital output (ground) 1. a ntenna d iversity rf switch control, see s ection 11.4 2. i f disabled, pull - down enabled (dvss) 10 dig2 digital output (ground) 1. a ntenna d iversity rf switch control ( dig1 inverted), see s ection 11.4 2. rx frame time stamping , see s ection 11.6 3 . tx frame time stamping , see s ection 11.6 4. if functions disabled, pull - down enabled (dvss) 11 slp_tr digital input controls sleep, deep sleep, transmit start, receive states; active high , see s ection 6.6 12 dvss ground digital ground 13 , 14 dvdd supply regulated 1.8v voltage regulator ; digital domain , see s ection 9.4 15 devdd supply external supply voltage ; digital domain 16 dvss ground digital ground 17 clkm digital output master clock signal output; low if disabled , see s ection 9.6 18 dvss ground digital ground 19 sclk digital input spi clock 20 miso digital output spi data output (master input slave output) 21 dvss ground digital ground 22 mosi digital input spi data input (master output slave input) 23 /sel digital input spi select, active low 24 irq digital output 1. interrupt request signal; active high or activ e low; configurable , see section 6.7 2. frame buffer empty indicator; active high, see s ection 11.7 25 xtal2 analog in put crystal pin , see s ection 9.6 26 xtal1 analog input crystal pin or external clock supply , see s ection 9.6 27 avss ground analog ground 28 evdd supply external supply voltage, analog domain 29 avdd supply regulated 1.8v voltage regulator ; analog domain , see s ection 9.4 30 , 31, 32 avss ground analog ground paddle avss ground analog ground ; exposed paddle of qfn package
4 8351b C C AT86RF233 1.2 analog and rf pins 1.2.1 supply and ground pins evdd, devdd evdd and devdd are analog and digital supply voltage pins of the atmel ? AT86RF233 radio transceiver. avdd, dvdd avdd and dvdd are outputs of the internal voltage regulators and require bypass capacitors for stable operation. the voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio tr ansceiver state. the voltage regulators can be configured for external supply; for details, refer to s ection 9.4 . avss, dvss avss and dvss are analo g and digital ground pins respectively. the analog and digital power domains should be separated on the pcb. 1.2.2 rf pins rfn, rfp a differential rf port (rfp/rfn) provides common - mode rejection to suppress the switching noise of the internal digital signal pro cessing blocks. at board - level, the differential rf layout ensures high receiver sensitivity by reducing spurious emissions originated from other digital ics such as a microcontroller. the rf port is designed for a 100 ? differential load. a n dc path betwee n the rf pins is allowed; an dc path to ground or supply voltage is not allowed . a simplified schematic of the rf front end is shown in figure 1 - 2 . figure 1 - 2 . simplified rf front - end schematic . l n a p a r x t x 0 . 9 v t x r x c m f e e d b a c k m 0 a t 8 6 r f 2 3 3 p c b
5 8351b C C AT86RF233 the rf port dc values depend on the operating state , see chapter 7 . in trx_off state , when the analog front - end is disabled (see s ection 7.1.2.5 ) , the rf pins are pulled to ground, preventing a floating voltage larger than 1.8v which is not allo wed for the internal circuitry. in transmit mode, a control loop provides a common - mode voltage of 0.9v. transistor m 0 is off, allowing the pa to set the common - mode voltage. the common - mode capacitance at each pin to ground shall be < 30 pf to ensure the stability of this common - mode feedback loop. in receive mode , the rf port provide s a low - impedance path to ground when transistor m0 , ( see figure 1 - 2 ) pulls the inductor center tap to ground. a n dc voltage drop of 20 mv across the on - chip inductor can be measured at the rf pins. 1.2.3 crystal oscillator pins xtal1, xtal2 the pin 26 ( xtal1 ) of atmel AT86RF233 is the input of the reference oscillator amplifier (xosc), the pin 25 ( xtal2 ) is the output. a detailed description of the crystal oscillator setup and the related xtal1 / xtal2 pin configuration can be found in s ection 9.6 . when u sing an extern al clock reference signal, xtal 1 shall be used as input pin. for further details, refer to s ection 9.6.3 . 1.2.4 analog pin summary table 1 - 2 . analog pin behavior C dc values . pin values and condition s comment s rfp/rfn v dc = 0.9v ( busy_ tx) v dc = 20 mv ( receive states ) v dc = 0 mv (otherwise) dc level at pins rfp/rfn for various transceiver states . ac coupling is required if a circuitry with dc path to ground or supply is used. serial capacitance and capacitance of each pin to ground must be < 30 pf . xtal1/xtal2 v dc = 0.9v at both pins c par = 3 pf dc level at pins xtal1/xtal2 for various transceiver states . parasitic capacitance (c par ) of the pins must be considered as additional load capacitance to the crystal. dvdd v dc = 1.8v (all states, except sleep and deep_ sleep) v dc = 0 mv (otherwise) dc level at pin dvdd for various transceiver states . supply pin s (voltage regulator output ) for the digital 1.8v voltage domain , recommended bypass capacitor 100 nf . avdd v dc = 1.8v (all states, except p_on, sleep, deep_sleep, reset, and trx_off) v dc = 0 mv (otherwise) dc level at pin avdd for various transceiver states . supply pin (voltage regulator output ) for the analog 1.8v voltage domain , recommended bypass capacitor 100 nf .
6 8351b C C AT86RF233 1.3 digital pins the atmel AT86RF233 provides a digital microcontroller interface. the interface comprises a slave spi (/ sel , sclk, mosi , and miso ) and additional control signals ( clkm, irq, slp_tr, /rst , and dig2 ) . the microcontroller interface is described in detail in c hapter 6 . additional digital output signals dig1 , , dig4 are provided to control external blocks , that is for antenna diversity rf switch control or as an rx/tx indicator , see s ection 11.4 and section 11.5 respectively . 1.3.1 driver strength settings the driver strength of all digital output pins (miso, irq , dig1 , , dig 4 ) and clkm pin are fixed. the capacitive load should be as small as possible as, not larger than 50 pf . 1.3.2 pull - up and pull - down configuration pulling transistors are internally connected to all digital input pins in radio transceiver state s p_on (including reset during p_on) and deep_sleep , see section 7.1.2.1 and section 7.1.2.4 . table 1 - 3 summarizes the pull - up and pull - down configuration. table 1 - 3 . pull - u p / pull - down configuration of digital i nput pins . pin h pull - up, l pull - down /rst h /sel h sclk l mosi l slp_tr (1) l note: 1. except slp_tr pin for deep_sleep state . in all other radio transceiver states , including reset , no pull - up or pull - down transistors are connected to any of the digital input pins mentioned in table 1 - 3 . note: 2. in all other states, external circuitry should guaranty defined levels at all input pins. floating input pins may cause unexpected functionality and increased power consumption, for ex ample in sleep state. if the additional digital output signals dig1 , , dig4 are not activated , these pins are pulled - down to digital ground (dig1/dig2) or analog ground (dig3/dig4). ? ? ? ?
7 8351b C C AT86RF233 2 disclaimer typical values contained in this datasheet are based on simulations and testing. min imum and m ax imum values are available when the radio transceiver has been fully characterized. 3 overview the atmel AT86RF233 is a feature rich, extremely low - power 2.4 ghz radio transceiver designed for industrial and consumer zigbee/ieee 802.15.4 , rf4ce, 6lowpan, and high data rate 2.4 ghz ism band applications. the radio transceiver is a true spi - to - antenna solution. all rf - critical components except the antenna, crystal and de - coupling capacitors are integrated on - chip. mac and aes hardware accelerators improve overall system power effici ency and timing. therefore, the AT86RF233 is particularly suitable for applications like: ? 2.4 ghz ieee 802.15.4 and zigbee system s ? rf4ce systems ? energy harvesting systems ? 6lowpan systems ? wireless sensor networks ? in dustrial control ? residential and commercial automation ? health care ? consumer electronics ? pc peripherals the AT86RF233 can be operated by using an external microcontroller like atmel avr ? microcontrollers. a compre hensive software programming description can be found in reference [ 7 ] .
8 8351b C C AT86RF233 4 general circuit description the atmel AT86RF233 single - chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. it comprises the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. the number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. the bidirectional differential antenna pins (rfp, rfn) are used for transmission and reception, thus no external antenna switch is ne eded. the AT86RF233 block diagram is shown in figure 4 - 1 . figure 4 - 1 . AT86RF233 block diagram . th e received rf signal at pin 5 ( rfn ) and pin 6 ( rfp ) is differentially fed through the low - noise amplifier (lna) to the rf filter (ppf) to generate a complex signal, driving the integrated channel filter (bpf). the limiting amplifier provides sufficient gain to drive the succeeding analog - to - digital convert er (adc) and generates a digital rssi signal. the adc output signal is sampled by the digital base band receiver (rx bbp). the transmit modulation scheme is offset - qpsk (o - qpsk) with half - sine pulse shaping and 32 - length block coding (spreading) according to [ 2 ] and [ 1 ] . the modulation signal is generated in the digital transmitter (tx bbp) and applied to the fractional - n frequency synthesis (pll), to ensure the coherent phase modulation required for a v r e g l n a p l l p a p p f b p f a d c a g c e x t . p a a n d p o w e r c o n t r o l c o n f i g u r a t i o n r e g i s t e r s s p i ( s l a v e ) r s s i i r q c l k m / r s t s l p _ t r / s e l m i s o m o s i s c l k d i g 3 / 4 r f p r f n t x d a t a c o n t r o l l o g i c d i g 2 a n t e n n a d i v e r s i t y f t n , b a t m o n x o s c x t a l 1 x t a l 2 a n a l o g d o m a i n d i g i t a l d o m a i n a e s d i g 1 / 2 a d d v r e g r x b b p f r a m e b u f f e r t x b b p l i m i t e r
9 8351b C C AT86RF233 demodulation of o - qpsk signals. the frequency - modulated signal is f ed to the power amplifier (pa). a differential pin pair dig3/dig4 can be enabled to control an external rf front - end. two on - chip low - dropout voltage regulators (a|dvreg) provide the analog and digital 1.8v supply. an internal 128 - byte ram for rx and tx (frame buffer) buffers the data to be transmitted or the received data. the configu ration of the atmel AT86RF233 , reading and writing of frame buffer is controlled by the spi interface and additional control lines. the AT86RF233 further contains compreh ensive hardware - mac support (extended operating mode) and a security engine (aes) to improve the overall system power efficiency and timing. the stand - alone 128 - bit aes engine can be accessed in parallel to all phy operational transactions and states using the spi interface, except during sleep and deep_sleep state s . for applications not necessarily targeting ieee 802.15.4 compliant networks, the radio transceiver also supports alter native data rates up to 2 000k b/s . for long - range applications or to improve the reliability of an rf connection the rf performance can further be improved by using an external rf front - end or antenna diversity. both operation modes are supported by the AT86RF233 with dedicated control pins without the interaction of the microcontroller. additional features of the extended feature set, see chapter 11 , are provided to simplify the interaction between radio transceiver and microcontroller.
10 8351b C C AT86RF233 5 application schematic 5.1 basic application schematic a basic application schematic of the atmel AT86RF233 with a sing le - ended rf connector is shown in figure 5 - 1 . the 50 single - ended rf input is transformed to the 100 differential rf port impedance using balun b1 . the capacitors c1 and c2 provi de ac coupling of the rf input to the rf port , optional capacitor c4 improves matching if required . figure 5 - 1 . basic application schematic . the p ower supply decoupling capacitors (cb2, cb4) are connected to the external analog supply pin 28 (evdd) and external digital supply pin 15 (devdd) . capacitors cb1 and cb3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. all bypass capacitors should be placed as close as possible to the pins and should have a low - resistance and low - inductance co nnection to ground to achieve the best performance. the crystal (xtal), the two load capacitors (cx1, cx2), and the internal circuitry connected to pins xtal1 and xtal2 form the crystal oscillator. to achieve the best accuracy and stability of the referenc e frequency, large parasitic capacitances should be avoided. crystal lines should be routed as short as possible and not in proximity of digital i/o signals. this is especially required for the high data rate modes; refer to s ection 11.3 . 8 7 6 5 4 3 2 1 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a t 8 6 r f 2 3 3 d i g 3 a v s s d i g 4 a v s s a v s s r f p r f n a v s s d v s s d i g 1 d i g 2 s l p _ t r d v s s d v d d d v d d x t a l 2 d e v d d d v s s a v s s a v d d e v d d a v s s x t a l 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 d v s s c l k m i r q m i s o d v s s m o s i s c l k c b 3 c b 4 d i g i t a l i n t e r f a c e / r s t / s e l v d d x t a l c x 1 c x 2 c b 1 v d d c b 2 c 1 c 2 b 1 r f c 3 r 1 c 4
11 8351b C C AT86RF233 crosstalk from digital signals on the crystal pins or the rf pins can degrade the system performance. therefore, a low - pass filter (c3, r 1 ) is placed close to the a tmel AT86RF233 clkm output pin to reduce the emission of clkm signal harmonics. this is not needed if the pin 17 ( clkm ) is not used as a microcontroller clock source . in that case, the output should be turned off during device initialization. the ground plane of the application board should be separated into four independent fragments: the analog, the digital, the antenna, and the xtal ground plane. the exposed paddle shall act as the reference point of the individual grounds. note: 1. the pins dig1, dig2, dig3, and dig4 are connected to ground in the basic application schematic; refer to figure 5 - 1 . special programming of these pins requires a different schematic; refer to section 5.2 . table 5 - 1 . exemplary bill of materials (bom) for basic application schematic . symbol description value manufacturer part number comment b1 smd balun 2.4 5 ghz wuerth 748421245 2.45 ghz balun b1 (alternatively) smd balun / filter 2.45 ghz johanson technology 2450fb15l0001 2.45 ghz balun / filter cb1 cb3 ldo vreg bypass capacitor 100 nf generic x7r (0402) 10% 16v cb2 cb4 power supply decoupling 1 f avx murata 0603yd105kat2a grm188r61c105ka12d x5r (0603) 10% 16v cx1, cx2 crystal load capacitor 12 pf avx murata 06035a120ja grm1555c1h120ja01d cog ( 0402 ) 5 % 50v c1, c2 rf coupling capacitor 22 pf murata epcos avx grm1555c1h220ja01j b37920 06035a220jat2a c0g 5% 50v (0402 or 0603) c3 clkm low - pass filter capacitor 2. 2 pf avx murata 06035a229da grp1886c1h2r0da01 cog (0603) ? 0. 5 pf 50 v designed for f clkm = 1 mhz c4 (optional) rf matching value depends on final pcb implementation r1 clkm low - pass filter resistor 680 ? designed for f clkm = 1 mhz xtal crystal cx - 4025 16 mhz sx - 4025 16 mhz acal taitjen siward xwbbpl - f - 1 a207 - 011
12 8351b C C AT86RF233 5.2 extended feature set application schematic the atmel AT86RF233 supports additional features like: ? security module (aes) s ection 11.1 ? random number generator s ection 11.2 ? high data rate mode s s ection 11.3 ? antenna diversity uses pins dig1(/2) s ection 11.4 ? rx /tx indicator uses pins dig3/4 s ection 11.5 ? rx and tx frame time stamping (tx_aret) uses pin dig2 s ection 11.6 ? frame buffer empty indicator uses pin irq s ection 11.7 ? dynamic frame buffer protection s ection 11.8 ? alternate start - of - frame delimiter s ection 11.9 ? reduce d power consumption mode (rpc) s ection 11.10 an extended feature set application schematic illustrating the use of the AT86RF233 extended feature set, see chapter 11 , is shown in figure 5 - 2 . although this ex ample shows all additional hardware features combined, it is possible to use all feature s separately or in various combinations . figure 5 - 2 . extended feature application schematic . 8 7 6 5 4 3 2 1 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a t 8 6 r f 2 3 3 d i g 3 a v s s d i g 4 a v s s a v s s r f p r f n a v s s d v s s d i g 1 d i g 2 s l p _ t r d v s s d v d d d v d d x t a l 2 d e v d d d v s s a v s s a v d d e v d d a v s s x t a l 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 d v s s c l k m i r q m i s o d v s s m o s i s c l k c b 3 c b 4 x t a l c x 1 c x 2 c b 1 d i g i t a l i n t e r f a c e v d d / r s t / s e l b a l u n a n t 0 r f - s w i t c h b 1 s w 1 s w 2 v d d c b 2 c 3 r 1 p a l n a n 1 n 2 a n t 1 r f - s w i t c h
13 8351b C C AT86RF233 in this example, a balun (b1) transforms the differential rf signal at the atmel AT86RF233 radio transceiver rf pins (rfp/rfn) to a single ended rf signal , similar to the basic application schematic; refer to figure 5 - 1 . during receive mode the radio transceiver searches for the most reliable rf signal path using the antenna diversity algorithm. one antenna i s selected (sw2) by the antenna diversity rf switch control pin 9 (dig1), refer to section 11.4 . t he rx signal is amplified by an optional low - nois e amplifier (n2) and fed to the radio transceiver using the rx/tx switch (sw1). during transmit mode the AT86RF233 tx signal is amplified using an external pa (n1) and fed to the antennas via an rf switch (sw2). t hese switch es are controlled by the rx/tx indicator, represented by the differential pin pair dig3/dig4 , refer to s ection 11.5 . rx and tx f rame t ime stamping is implemented through pin 10 (dig2) , refer to s ection 11.6 . the security module (aes) , random number generator , high data rate mode s , frame buffer empty indicator , dynamic frame buffer protection , alternate start - of - frame delimiter or reduce d power consumption mode (rpc) do not require specific circuitry to operate , for details refer to s ection 11.1 , section 11.2 , section 11.3 , section 11.7 , section 11.8 , section 11.9 and section 11.10 .
14 8351b C C AT86RF233 6 microcontroller interface 6.1 overview this section describes the atmel AT86RF233 to microcontroller interface. the interface comprises a slave spi and additional control signals; see figure 6 - 1 . the spi timing and protocol are described below . figure 6 - 1 . microcontroller to AT86RF233 interface . microcontrollers w ith a master spi such as atmel avr family interface directly to the AT86RF233 . the spi is used for register, frame buffer , sram and aes access. the additional control signals are connected to the gpio/irq interface of the microcontroller. table 6 - 1 introduces the radio transceiver i/o signals and the ir functionality. table 6 - 1 . signal description of microcontroller interface . signal description /sel spi select signal , active low mosi spi data (master output slave input) signal miso spi data (master input slave output) signal sclk spi clock signal clkm optional, clock output, refer to s ection 9.6.4 , usable as: - microcontroller clock source - high precision timing reference irq interrupt request signal , further used as: - frame buffer empty indicator, refer to section 11.7 slp_tr multi purpose control signal ( functionality is state dependent , see section 6.6 ): - s l eep/wakeup enable/disable sleep state - sleep/wakeup enable/disable deep_sleep state - tx start busy_tx _(aret) state /rst AT86RF233 r eset signal , active low dig2 optional, - irq_2 ( rx_start ) for rx frame time stamping, see section 11.6 - signals frame transmit within t x _aret mode for tx time stamping m i c r o c o n t r o l l e r a t 8 6 r f 2 3 3 / s e l m o s i m i s o s c l k c l k m i r q s l p _ t r m o s i m i s o s c l k g p i o 1 / c l k g p i o 2 / i r q g p i o 3 m o s i m i s o s c l k c l k m i r q s l p _ t r / r s t g p i o 4 s p i / s e l / s e l / r s t d i g 2 g p i o 5 d i g 2 s p i - m a s t e r s p i - s l a v e
15 8351b C C AT86RF233 6.2 spi timing description pin 17 ( clkm ) can be used as a microcontroller master clock source. if the microcontroller derives the spi master clock (sclk) directly from clkm, the spi operates in synchronous mode, otherwise in asynchronous mode. in asynchronous mode, the maximum sclk frequency f async is lim ited to 7.5 mhz . the signal at pin 17 ( clkm ) is not required to derive sclk and may be disabled to r educed p ower c onsumption and spurious emissions. figure 6 - 2 and figure 6 - 3 illustrate the spi timing and introduces its parameters. the corresponding timing parameter definition s t 1 C t 9 are defined in section 12.4 . figure 6 - 2 . spi timing, g lobal map and definition of timing parameters t 5 , t 6 , t 8 , t 9 . figure 6 - 3 . spi timing, d etail ed drawing of timing parameter s t 1 to t 4 . the spi is based on a byte - oriented protocol and is always a bidirectional communication between the master and slave. the spi master starts the transfer by asserting /sel = l. then the master generates eight spi clock cycles to transfer one byte to the radio transceiver (via mosi). at the same time, the slave transmits one byte to the master (via miso). when the master wants to receive one byte of data from the slave , it must also transmit one byte to the slave. all bytes are transferred with the msb first. an spi transaction is finished by releasing /sel = h. an spi register access consists of two bytes, a frame buffer or sram access of at least two or more bytes as described in section 6.3 . / sel = l enables the miso output driver of the atmel AT86RF233 . the msb of miso is valid after t 1 (see section 12.4 ) and is updated on each sclk falling edge . if the driver is disabled, there is no internal pull - up transistor connected to it. driving the appropriate signal level must be ensured by the master device or an external pull - up resistor. sclk t 8 mosi 6 7 5 4 3 2 1 0 6 7 5 4 3 2 1 0 miso bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 bit 4 bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 bit 4 bit 7 t 6 bit 7 t 5 / sel t 9 bit 7 bit 6 t 1 t 2 bit 5 t 4 t 3 bit 7 bit 6 bit 5 sclk mosi miso / sel
16 8351b C C AT86RF233 note: 1. w hen both /sel and / rst are active , the miso output driver is also enabled. referring to figure 6 - 2 and figure 6 - 3 , atmel AT86RF233 mosi is sam pled at the rising edge of the sclk signal and the output is set at the falling edge of sclk. the signal must be stable before and after the rising edge of sclk as specified by t 3 and t 4 , refer to s ection 12.4 parameters . this spi operational mode is commonly known as D spi mode 0 . 6.3 spi protocol each spi sequence starts with transferring a command byte from the spi master via mosi (see table 6 - 2 ) with the msb first . this command byte defines the spi access mode and additio nal mode - dependent information. table 6 - 2 . spi command byte defini tion . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access mode access type 1 0 register address [5:0] register access read access 1 1 register address [5:0] write access 0 0 1 r eserved frame buffer access read access 0 1 1 r eserved write access 0 0 0 r eserved sram access read access 0 1 0 r eserved write access each spi transfer return s byte s back to the spi master on miso . the content of the first byte ( see value D phy _status D in figure 6 - 4 to figure 6 - 14 ) is set to zero after reset. to transfer status information of the radi o transceiver to the microcontroller , the content of the first byte can be configured with register bits spi_cmd_mode ( register 0x 04 , trx_ctrl_1 ) . for details, refer to s ection 6.4.1 . note: 1. return values on miso stated as xx shall be ignored by the microcontroller. the different access modes are described within the following sections. 6.3.1 register access mode r egister a ccess m ode is used to read and write AT86RF233 resisters (register address from 0x00 up to 0x3f). a r egister access mode is a two - byte read/write operation initiated by /sel = l . the first transferred byte on mosi is the command byte including an identifier bit ( b it [ 7 ] = 1 ) , a read/write select bit ( b it [ 6 ] ) , and a 6 - bit register address. on read access, the conte nt of the selected register address is returned in the second byte on miso (see figure 6 - 4 ). figure 6 - 4 . packet structure - register read access . note: 1. each spi access can be configured to return radio controller status information ( phy _status ) on miso, for details refer to section 6.4 . 1 address [ 5 : 0 ] 0 xx mosi phy _ status ( 1 ) read data [ 7 : 0 ] miso byte 1 ( command byte ) byte 2 ( data byte )
17 8351b C C AT86RF233 on write access , the second byte transferred on mosi contains the write data to the selected address (see figure 6 - 5 ). figure 6 - 5 . packet structure - register write access . each register access must be terminated by setting /sel = h. figure 6 - 6 illustrates a typical spi sequence for a register access sequence for write and read respectively. figure 6 - 6 . example spi sequence C register access mode . 6.3.2 frame buffer access mode frame buffer access mode is used to read and write atmel AT86RF233 frame buffer. the frame buffer address is always reset to zero and incremented to access psdu, lqi, ed and rx_status data. the 128 - byte frame buffer can hold the phy service data unit ( psdu ) data of one ieee 802.15.4 compliant r x or one t x frame of maximu m length at a time. a detailed description of the frame buffer can be found in section 9.3 . an introduction to the ieee 802.15.4 frame format can be found in section 8.1 . ea ch access starts with /sel = l followed by a command byte on mosi. each frame read or write access command byte is followed by the phr data byte, indicating the frame length , followed by the psdu data, see figure 6 - 7 and figure 6 - 8 . in frame buffer access mode during buffer reads, the phy header (phr) and the psdu data are transferred via miso following phy_status byte. once the psdu data is uploaded, three more bytes a re transferred containing the link quality indication (lqi) value, the energy detection (ed) value, and the status information (rx_status) of the received frame, for lqi details refer to section 8.6 . the figure 6 - 7 illustrates the packet structure of a frame buffer read access. note: 1. t he f rame b uffer read access can be terminated immediately at any time by setting pin 23 ( /sel ) = h, for example after reading the phr byte only. 1 address [ 5 : 0 ] 1 write data [ 7 : 0 ] mosi phy _ status xx miso byte 1 ( command byte ) byte 2 ( data byte ) phy _ status xx phy _ status read data write command write data read command xx register write access register read access sclk mosi miso / sel
18 8351b C C AT86RF233 figure 6 - 7 . packet structure - frame read access . the structure of rx_status is described in table 6 - 3 . table 6 - 3 . structure of rx_status . bit 7 6 5 4 rx_crc_valid trac_status rx_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 reserved rx_status read/write r r r r reset value 0 0 0 0 note: 2 . more information to rx_crc_valid , see section 8.2.5 , an d to trac_status, see section 7.2.6 . on f rame b uffer write access the second byte transferred on mosi contains the frame length (phr field) follo wed by the payload data (psdu) as shown by figure 6 - 8 . figure 6 - 8 . packet structure - frame write access . the number of bytes n for one frame buffer access is calculated as follows: read access : n = 5 + frame_length [ ph y _status , phr byte, psdu data , lqi, ed, and rx_status ] write access : n = 2 + frame_length [command byte, phr byte, and psdu data] the maximum value of frame_length is 127 bytes. that means that n 132 for frame buffer read and n 129 for frame buffer write accesses. each read or write of a data byte automatically increments the address counte r of the frame buffer until the access is terminated by setting /sel = h . a frame buffer read access can be terminated at any time without any consequences by setting /sel = h , for exemple after reading the frame length byte only. a successive frame buffer read operation starts again with the phr field. the content of the atmel AT86RF233 frame buffer is overwritten by a new received frame or a frame buffer w rite a ccess. figure 6 - 9 and figure 6 - 10 illustrate an example spi sequence of a frame buffer ac cess to read a frame with 2 - byte psdu and write a frame with 4 - byte psdu . 0 r e s e r v e d [ 4 : 0 ] 0 m o s i p h y _ s t a t u s m i s o b y t e 1 ( c o m m a n d b y t e ) 1 x x p h r [ 7 : 0 ] b y t e 2 ( d a t a b y t e ) x x p s d u [ 7 : 0 ] b y t e 3 ( d a t a b y t e ) x x e d [ 7 : 0 ] b y t e n - 1 ( d a t a b y t e ) x x r x _ s t a t u s [ 7 : 0 ] b y t e n ( d a t a b y t e ) 0 r e s e r v e d [ 4 : 0 ] 1 m o s i p h y _ s t a t u s m i s o b y t e 1 ( c o m m a n d b y t e ) 1 p h r [ 7 : 0 ] x x b y t e 2 ( d a t a b y t e ) p s d u [ 7 : 0 ] x x b y t e 3 ( d a t a b y t e ) p s d u [ 7 : 0 ] x x b y t e n - 1 ( d a t a b y t e ) p s d u [ 7 : 0 ] x x b y t e n ( d a t a b y t e )
19 8351b C C AT86RF233 figure 6 - 9 . example spi sequence - frame buffer read of a frame with 2 - byte psdu . figure 6 - 10 . example spi sequence - frame buffer write of a frame with 4 - byte psdu . access violations during a frame buffer read or write access are indicated by interrupt irq_6 ( trx_ur ) . for further details, refer to section 9.3 . notes: 1. the frame buffer is shared be tween rx and tx operations, the frame data is overwritten by freshly received data frames. if an existing tx payload data frame is to be retransmitted, it must be ensured that no tx data is overwritten by newly received rx data . 2. to avoid overwriting during receive dynamic frame buffer protection can be enabled, refer to section 11.8 . 3. for exceptions, receiving acknowledgement frames in extended operati ng mode (tx_aret) refer to section 7.2.4 . 6.3.3 sram access mode the sram access mode is used to read and write atmel AT86RF233 frame buffer beginning with a specified byte address. it enables to access dedicated buffer data directly from a desired address without a need of incrementing the frame buffer from the top. the sram access mode allows accessing dedicated bytes within the frame buffer or aes address space , refer to section 11.1 . this may reduce the spi traffic. during frame receive , after occurrence of irq_2 ( rx_start ) , an sram access can be used to upload the phr field while preserving dynamic frame buffer protection, see section 11.8 . each sram access starts with /sel = l. the first transferred byte on mosi shall be the command byte and must indicate a n sram access mode according to the definition in table 6 - 2 . the following byte indicates the start address of the write or read access. sram address space: ? frame buffer: 0x00 to 0x7f ? aes: 0x82 to 0x94 c o m m a n d x x x x x x x x x x p h y _ s t a t u s p h r p s d u 2 p s d u 1 e d l q i x x r x _ s t a t u s s c l k m o s i m i s o / s e l command phr psdu 1 psdu 2 psdu 3 psdu 4 phy _ status xx xx xx xx xx sclk mosi miso / sel
20 8351b C C AT86RF233 on sram read access , one or more bytes of read data are transferred on miso starting with the third byte of the access sequence (see figure 6 - 11 ). figure 6 - 11 . pack et structure C sram read access . on sram write access , one or more bytes of write data are transferred on m o s i starting with the third byte of the access sequence (see figure 6 - 12 ). do not attempt to read or write bytes beyond the sram buffer size. figure 6 - 12 . packet structure C sram write access . as long as /sel = l , every subsequent byte read or byte write increments the address counter of the frame buffer until the sram access is terminated by /sel = h . figure 6 - 13 and figure 6 - 14 illustrate an example spi sequence of a n atmel AT86RF233 sram access to read and write a data package of 5 - byte length respectively. figure 6 - 13 . example spi sequence C sram read access of a 5 - byte data package . figure 6 - 14 . example spi se quence C sram write access of a 5 - byte data package . 0 r e s e r v e d [ 4 : 0 ] 0 m o s i p h y _ s t a t u s m i s o b y t e 1 ( c o m m a n d b y t e ) 0 a d d r e s s [ 7 : 0 ] x x b y t e 2 ( a d d r e s s ) x x d a t a [ 7 : 0 ] b y t e 3 ( d a t a b y t e ) x x d a t a [ 7 : 0 ] b y t e n - 1 ( d a t a b y t e ) x x d a t a [ 7 : 0 ] b y t e n ( d a t a b y t e ) 0 r e s e r v e d [ 4 : 0 ] 1 m o s i p h y _ s t a t u s m i s o b y t e 1 ( c o m m a n d b y t e ) 0 a d d r e s s [ 7 : 0 ] x x b y t e 2 ( a d d r e s s ) d a t a [ 7 : 0 ] x x b y t e 3 ( d a t a b y t e ) d a t a [ 7 : 0 ] x x b y t e n - 1 ( d a t a b y t e ) d a t a [ 7 : 0 ] x x b y t e n ( d a t a b y t e ) command address xx xx xx xx phy _ status xx data 2 data 1 data 4 data 3 xx data 5 sclk mosi miso / sel command address data 1 data 2 data 3 data 4 phy _ status xx xx xx xx xx data 5 xx sclk mosi miso / sel
21 8351b C C AT86RF233 notes: 1. the sram access mode is not intended to be used as an alternative to the frame buffer access modes (see section 6.3.2 ). 2. frame buffer access violations are not indicated by a trx_ur interrupt when using the sram access mode, for further details refer to section 9.3.3 . 6.4 radio transceiver status information each atmel AT86RF233 spi access can be configured to return status information of the radio transceiver ( p hy _status ) to the microcontroller using the first byte of the data transferred via miso. the content of the radio transceiver status information can be configured using register bits spi_cmd_mode ( register 0x 04, trx_ctrl_1) . after reset, the content on the first byte send on miso to the microcontroller is set to zero . 6.4.1 register description note: 1. throughout this datasheet, underline d values indicate reset settings. register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver. figure 6 - 15 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 3:2 - spi_cmd_mode each spi transfer returns bytes back to the spi master. the content of the first byte (phy_status) can be configured using register bits spi_cmd_mode. table 6 - 4 . spi_cmd_mode. register bits value description spi_cmd_mode 0 default (empty, all bits zero) 1 monitor trx_status register 2 monitor phy_rssi register 3 monitor irq_status register note: 2 . more information to register trx_status , see s ection 7.1.5 , to register phy_rssi , see s ection 8.3 , and to register irq_status , see s ection 6.7 .
22 8351b C C AT86RF233 6.5 radio transceiver identification the atmel AT86RF233 can be identified by four registers. one register contains a unique part number and one register the corresponding version number. additional two registers contain the jedec manufacture id. 6.5.1 register descri ption register 0x1c (part_num): the register part_num can be used for the radio transceiver identification and includes the part number of the device. figure 6 - 16 . register part_num. bit 7 6 5 4 0x1c part_num part_num read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x1c part_num part_num read/write r r r r reset value 1 0 1 1 ? bit 7:0 - part_num table 6 - 5 . part_num. register bits value description part_num 0x0b AT86RF233 part number register 0x1d (version_num): the register version_num can be used for the radio transceiver identification and includes the version number of the device. figure 6 - 17 . register version_num. bit 7 6 5 4 0x1d version_num version_num read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x1d version_num version_num read/write r r r r reset value 0 0 0 1 ? bit 7:0 - version_num table 6 - 6 . version_num. register bits value description version_num 0x01 revision a
23 8351b C C AT86RF233 register 0x1e (man_id_0): part one of the jedec manufacturer id. figure 6 - 18 . register man_id_0. bit 7 6 5 4 0x1e man_id_0 man_id_0 read/write r r r r reset value 0 0 0 1 bit 3 2 1 0 0x1e man_id_0 man_id_0 read/write r r r r reset value 1 1 1 1 ? bit 7:0 - man_id_0 table 6 - 7 . man_id_0. register bits value description man_id_0 0x1f atmel jedec manufacturer id, bits[7:0] of the 32 - bit jedec manufacturer id are stored in register bits man_id_0. bits [15:8] are stored in register 0x1f (man_id_1). the higher 16 bits of the id are not stored in registers. register 0x1f (man_id_1): part two of the jedec manufactu rer id. figure 6 - 19 . register man_id_1. bit 7 6 5 4 0x1f man_id_1 man_id_1 read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x1f man_id_1 man_id_1 read/write r r r r reset value 0 0 0 0 ? bit 7:0 - man_id_1 table 6 - 8 . man_id_1. register bits value description man_id_1 0x00 atmel jedec manufacturer id, bits[15:8] of the 32 - bit jedec manufacturer id are stored in register bits man_id_1. bits [7:0] are stored in register 0x1e (man_id_0). the higher 16 bits of the id are not stored in registers.
24 8351b C C AT86RF233 6.6 sleep/wake - up and transmit signal (slp_tr) pin 11 ( slp_tr ) is a multi - functional pin. its function relates to the current state of the atmel AT86RF233 and is summarized in table 6 - 9 . the radio transceiver states are explained in detail in chapter 7 . table 6 - 9 . slp_tr multi - functional pin . transceiver status function transition description pll_on tx start l ? h s tarts frame transmission tx_aret_on tx start l ? h s tarts tx_aret transaction busy_rx_aack tx start l ? h starts ack transmission during rx_aack slotted operation, see section 7.2.3.5 trx_off sleep l ? h takes the radio transceiver into sleep state , clkm disabled prep_deep_sleep deep sleep l ? h takes the radio transceiver into deep_sleep state, clkm disabled sleep wakeup h ? l takes the radio transceiver back into trx_off state, level sensitive deep_sleep wakeup h ? l takes the radio transceiver back into trx_off state, level sensitive in states pll_on and tx_aret_on, pin 11 ( slp_tr ) is used as trigger input to initiate a tx transaction. here slp_tr is sensitive on rising edge only . after initiating a state change by a rising edge at pin 11 ( slp_tr ) in radio transceiver states trx_off or prep_deep_sleep , t he radio transceiver remain s in the new state as long as the pin is logical high and returns to the preceding state with the falling edge. sleep state the sleep state is used when radio transceiver functionality is not required, and thus the AT86RF233 can be powered down to reduce the overall power consumption. a power - down scenario is shown in figure 6 - 20 . when the radio transceiver is in trx_off state t he microcontroller force s the AT86RF233 to sleep by setting slp_tr = h. if pin 17 ( clkm ) provides a clock to the microcontroller this clock is switched off after 35 clkm cycles . this enables a microcontroller in a synchronous system to complete its power - down routine and prevent deadlock situations. the AT86RF233 awakes when the microcontroller releases pin 11 ( slp_tr ) . this concept provides the lowest possible power consumption. the clkm clock frequency settings for 250 khz and 62.5 khz are not intended to directly clock the microcontroller. when using these clock rates , clkm is turned off immediately when entering sleep s tate . figure 6 - 20 . sleep and wake - up initiated by asynchronous microcontroller timer . note: 1. timing figures t tr3 and t tr1a refer to table 7 - 1 . c l k m s l p _ t r t t r 3 ( 3 5 c l k m c l o c k c y c l e s ) c l k m o f f t t r 1 a a s y n c t i m e r e l a p s e s ( m i c r o c o n t r o l l e r )
25 8351b C C AT86RF233 deep_sleep state the deep_sleep state is used when radio transceiver functionality is not required, and thus the atmel AT86RF233 can be powered down to reduce the overall power consumption. when the radio transceiver is in prep_deep_sleep state the microcontroller forces the AT86RF233 to deep_sleep by setting slp_tr = h. if pin 17 (clkm) provides a clock to the microcontroller this clock is switched off after 35 clkm cycles . this en ables a microcontroller in a synchronous system to complete its power - down routine and prevent deadlock situations. the AT86RF233 awakes when the microcontroller releases pin 11 ( slp_tr ) and goes into trx_off state . this concept provides the lowest possible power consumption. the clkm clock frequency settings for 250 khz and 62.5 khz are not intended to directly clock the microcontroller. when using these clock rates, clkm is turned off imme diately when entering deep_sleep state. note: 1. after leaving the deep_sleep state the clkm clock frequency is set back to 1 mhz .
26 8351b C C AT86RF233 6.7 interrupt logic 6.7.1 overview the atmel AT86RF233 differentiate s between nine interrupt events (eight physical interrupt registers, one shared by two functions) . each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x 0e ( irq_mask ). internally, each pending interrupt is stored in a separate bit of the interrupt status register. all interrupt events are or - combined to a single external interrupt signal ( irq pin ) . if an i nterrupt is issued , pin 24 ( irq ) = h , the microcontroller shall read the interrupt status register 0x 0f ( irq_status ) to determine the source of the interrupt. a read access to this register clears the interrupt status register and thus the irq pin , too . interrupts are not cleared automatically when the re spective interrupt flag bit in the register 0x0f ( irq_status ) are not read and when the event trigger is no longer active . exceptions are irq_0 ( pll_lock ) and irq_1 ( pll_unlock ) because the occu rrence o f one clears the other. the supported interrupts for the basic operating mode are summarized in table 6 - 10 . table 6 - 10 . interrupt description in basic operating mode . irq name description section irq_7 ( bat_low ) indicates a supply voltage below the programmed threshold. 9.5.4 irq_6 ( trx_ur ) indicates a frame buffer access violation. 9.3.3 irq_5 ( ami ) indicates an address match . 7.2.3.4 irq_ 4 ( cca_ed_done ) multi - functional interrupt: 1. awake_end: ? indicates finished transition to trx_off state from p_on, sleep, deep_sleep, or reset state . 2. cca_ed_done : ? indicates the end of a cca or ed measurement . 7.1.2.5 8.4.4 8.5.4 irq_3 ( trx_end ) rx: indicates the completion of a frame reception. tx: indicates the completion of a frame transmission. 7 .1.3 7.1.3 irq_2 ( rx_start ) indicates the start of an psdu reception; the AT86RF233 state changed to busy_rx; the phr can be read from frame buffer. 7.1.3 irq_1 ( pll_unlock ) indic ates pll unlock. if the radio transceiver is in busy_tx / busy_tx_aret state, the pa is turned off immediately . 9.7.5 irq_0 ( pll_lock ) indicates pll lock . 9.7.5 note: 1. the irq_4 (awake_end) interrupt can usually not be seen when the transceiver enters trx_off state after p_on, deep_sleep, or reset , because register 0x0e (irq_mask) is reset to mask all interrupts. it is recommended to enable irq_4 (awake_end) to be notified once the trx_off state is entered. the interrupt handling in extended operating mode is described in section 7.2.5 .
27 8351b C C AT86RF233 6.7.2 interrupt mask modes and pin polarity if register bit irq_mask_mode ( register 0x 04, trx_ctrl_1) is set, an interrupt event can be read from irq_status register even if the interrupt itself is masked. however, in that case no timing information for this interrupt is provided. the table 6 - 11 , figure 6 - 21 , and figure 6 - 22 describes the function. table 6 - 11 . irq mask configuration . irq_mask value irq_mask_mode description 0 0 irq is suppressed entirely and none of interrupt causes are shown in register irq_status. 0 1 irq is suppressed entirely but all interrupt causes are shown in register irq_status. 0 0 all enabled interrupts are signaled on irq pin and are also shown in register irq_status. 0 1 all enabled interrupts are signaled on irq pin and all interrupt causes are shown in register irq_status. figure 6 - 21 . irq_mask_mode = 0 . figure 6 - 22 . irq_mask_mode = 1 . the atmel AT86RF233 irq pin polarity can be configured with register bit irq_polarity ( register 0x 04, trx_ctrl_1). the default behavior is active high , which means that pin 24 ( irq ) = h issues an interrupt request. if the Dframe buffer empty indicator is enabled during frame buffer r ead access , the irq pin has a n alternative functionality , r efer to section 11.7 for details. a solution to monitor the irq_status register (withou t clearing it) is described in section 6.4.1 . irq _ mask ( register 0 x 0 e ) irq _ status ( register 0 x 0 f ) or irq i n t e r r u p t s o u r c e s . . . or irq i n t e r r u p t s o u r c e s irq _ mask ( register 0 x 0 e ) . . . irq _ status ( register 0 x 0 f )
28 8351b C C AT86RF233 6.7.3 register description register 0x0e (irq_mask): the irq_mask register controls the interrupt signaling via pin 24 (irq). figure 6 - 23 . register irq_mask. bit 7 6 5 4 0x0e irq_mask irq_mask read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x0e irq_mask irq_mask read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:0 - irq_mask mask register for interrupts. irq_mask[7] correspondents to irq_7 (bat_low). irq_mask[0] correspondents to irq_0 (pll_lock). table 6 - 12 . irq_mask. register bits value description irq_mask 0x00 the irq_mask register is used to enable or disable individual interrupts. an interrupt is enabled if the corresponding bit is set to one. all interrupts are disabled after power - on sequence (p_on or deep_sleep state) or reset (reset state). valid values ar e [0xff, 0xfe, , 0x00]. note: 1. if an interrupt is enabled it is recommended to read the interrupt status register 0x0f (irq_status) first to clear the history. register 0x0f (irq_status): the irq_status register contains the status of the pending interrupt requests. figure 6 - 24 . register irq_status. bit 7 6 5 4 0x0f irq_7_bat_low irq_6_trx_ur irq_5_ami irq_4_cca_ed_ done irq_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x0f irq_3_trx_end irq_2_rx_ start irq_1_pll_ unlock irq_0_pll_ lock irq_status read/write r r r r reset value 0 0 0 0 for more information to meanings of interrupts, see table 6 - 10 interrupt description in basic operating mode .
29 8351b C C AT86RF233 by reading the register after an interrupt is signaled at pin 24 (irq) the source of the issued interrupt can be identified . a read access to this register reset s all interrupt bits , and so clears the irq_status register . note s : 1. if register bit irq_mask_mode (register 0x04, trx_ctrl_1) is set, an interrupt event can be read from irq_status register even if the interrupt itself is masked ; refer to figure 6 - 22 . however in that case no timing information for this interrupt is provided. 2. if regis ter bit irq_mask_mode (register 0x04, trx_ctrl_1) is set, it is recommended to read the interrupt status re gister 0x0f (irq_status) first to clear the history. register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver. figure 6 - 25 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 6 - irq_2_ext_en the register bit irq_2_ext_en controls external signaling for time stamping via pin 10 (dig2). table 6 - 13 . irq_2_ext_en. register bits value description irq_2_ext_en 0 time stamping over pin 10 (dig2) is disabled 1 (1) time stamping over pin 10 (dig2) is enabled notes: 1. the pin 10 (dig2) is also active if the corresponding interrupt event irq_2 (rx_start) mask bit in register 0x0e (irq_mask) is set to zero. 2. the pin remains at high level until the end of the frame receive or transmit procedure. the timing of a received frame can be determined by a separate pin 10 (dig2) . if register bit irq_2_ext_en is set to one , the reception of a phr field is directly issued on pin 10 (dig2) , similar to interrupt irq_2 ( rx_start ) . for further details refer to section 11.6 .
30 8351b C C AT86RF233 ? bit 1 - irq_mask_mode the radio transceiver supports polling of interrupt events. interrupt polling is enabled by setting register bit irq_mask_mode. table 6 - 14 . irq_mask_mode. register bits value description irq_mask_mode 0 interrupt polling is disabled. masked off irq bits will not appear in irq_status register. 1 interrupt polling is enabled. masked off irq bits will appear in irq_status register. with the interrupt polling enabled (irq_mask_mode = 1) the interrupt events are flagged in the register 0x0f (irq_status) when their respective mask bits are disabled in the register 0x0e (irq_mask) . ? bit 0 - irq_polarity the register bit irq_polarity controls the polarity for pin 24 (irq). the default polarity of the pin 24 (irq) is active high. the polarity can be configured to active low via register bit irq_polarity. table 6 - 15 . irq_polarity. register bits value description irq_polarity 0 pin irq is high active 1 pin irq is low active note: 1. a modification of register bit irq_polarity has no influence to rx_bl_ctrl behavior. this setting does not affect the polarity of the Dframe buffer empty indicator , refer to section 11.7 . the frame buffer empty indicator is always active high .
31 8351b C C AT86RF233 7 operating modes 7.1 basic operating mode this section summarizes all states to provide the basic functionality of the atmel AT86RF233 , such as receiving and transmitting frames, the power - on sequence , sleep and deep sleep . the basic operating mode is designed for ieee 802.15.4 and general i sm band applications; the corresponding radio transceiver states are shown in figure 7 - 1 . figure 7 - 1 . basic op erating mode state diagram ( for timing refer to table 7 - 1 ) . p l l _ o n r x _ o n p l l _ o n t r x _ o f f ( c l o c k s t a t e ) x o s c = o n p u l l = o f f r x _ o n ( a l l s t a t e s e x c e p t p _ o n ) f o r c e _ t r x _ o f f ( a l l s t a t e s e x c e p t s l e e p o r d e e p _ s l e e p ) s h r d e t e c t e d f r a m e e n d f r a m e e n d b u s y _ t x ( t r a n s m i t s t a t e ) p l l _ o n ( p l l s t a t e ) t x _ s t a r t o r t r x _ o f f t r x _ o f f 4 5 7 6 8 9 1 1 1 0 1 2 1 3 / r s t = h f o r c e _ p l l _ o n ( a l l s t a t e s e x c e p t d e e p _ s l e e p , s l e e p , o r p _ o n ) 1 4 s l p _ t r = h l e g e n d : b l u e : s p i w r i t e t o r e g i s t e r t r x _ s t a t e ( 0 x 0 2 ) r e d : c o n t r o l s i g n a l s v i a i c p i n g r e e n : e v e n t b a s i c o p e r a t i n g m o d e s t a t e s s t a t e t r a n s i t i o n n u m b e r , s e e t a b l e 7 - 1 f o r t i m i n g r x _ o n ( r x l i s t e n s t a t e ) b u s y _ r x ( r e c e i v e s t a t e ) r e s e t x ( f r o m a l l s t a t e s ) / r s t = l 2 t r x _ o f f s l p _ t r = h 3 p _ o n ( p o w e r - o n a f t e r v d d ) x o s c = o n p u l l = o n s l e e p ( s l e e p s t a t e ) x o s c = o f f p u l l = o f f s l p _ t r = l d e e p _ s l e e p ( s l e e p s t a t e ) x o s c = o f f p u l l = o n s l p _ t r = h x o s c = o n p u l l = o f f p r e p _ d e e p _ s l e e p ( p r e p a r e s l e e p s t a t e ) s l p _ t r = l t r x _ o f f p r e p _ d e e p _ s l e e p 1 5 1 6 1 7 1 8 1 9
32 8351b C C AT86RF233 7.1.1 state control the radio transceiver s states are controlled by shifting serial digital data using the spi to writ e individual commands to the command register b its trx_cmd (register 0x02, trx_state ). change of the transceiver state can also be triggered by driving directly two signal pins : pin 11 (slp_tr) and pin 8 (/rst) . a successful state change can be verified by reading the radio transceiver status from register bits trx_status (register 0x01, trx_status). if trx_status = 0x1f (state_transition_in_progress) the atmel AT86RF233 is in a state transition. do not try to initiate a further state change while the radio transceiver is in state_transition_in_progress. pin 11 (slp_tr) is a mult ifunctional pin , refer to section 6.6 . depending on the radio transceiver state , a rising edge of pin 11 ( slp_tr ) causes the following state transitions: ? trx_off ? sleep (level sensitive) ? pll_on ? busy_tx ? prep_ deep_sleep ? deep_sleep (level sensitive) whereas the f alling edge of pin slp_tr causes the following state transitions: ? sleep ? trx_off (level sensitive) ? deep_sleep ? trx_off (level sensitive) a low level on p in 8 (/rst) causes a reset of all registers (register bits clkm_ctrl are shadowed, for details , refer to section 9.6.4 ) and forces the radio transceiver into trx_off state. however, if the device was in p_on state it remains in the p_on state. for all states except sleep and deep_sleep , the state change commands force_trx_off or trx_off lead to a transition into trx_off state. if the radio transceiver is in active receive or transmit states (busy_*) , the command force_trx_off interrupts the se active process es , and forces an immediate transition to trx_off . in contrast a trx_off command is stored until a n active state (receiving or transmitting) has been finished. after th at the transition to trx_off is performed . for a fast transition from any non sleep states to pll_on state the command force_pll_ on is provided . in contrast to force_trx_off , this command does not disable pll and analog voltage regulator ( avreg ) . it is not available in states p_on, sleep, deep_sleep, or reset . the completion of each requested state change shall always be confirmed by reading the register bits trx_status ( register 0x 01, trx_status). note: 1. if force_trx_off and force_pll_on commands are used, it is recommended to set pin 11 (slp_tr) = l before . 7.1.2 basic operating mode description 7.1.2.1 p_on C power - on after v dd when the external supply voltage (v dd ) is first ly applied to the AT86RF233 , the radio transceiver goes in to p_on state performing an on - chip reset. the crystal oscillator is activated and t he default 1 mhz master c lock is provided at pin 17 ( clkm ) after the
33 8351b C C AT86RF233 crystal oscillator has stabilized. clkm can be used as a clock source to the microcontroller. the spi interface and digital voltage regulator (dvreg) are enabled. the on - chip power - on - reset sets all registers to their default values. a dedicated reset signal from the microcontroller at pin 8 ( /rst ) is not necessary, but recommended for hardware / software synchronization reasons. all digital inputs are pulled - up or pulled - down during p_on state , refer to section 1.3.2 . this is necessary to support microcontrollers where gpio signals are floating after power - on or reset. the input pull - up and pull - down circuit ry is disabled when the radio transceiver leaves the p_on state . o utput pins dig1 /dig2 are pulled - down to digital ground , wherea s pins dig3/dig4 are pulled - down to analog ground, unless their configuration is changed . prior to leaving p_on, the microcontroller must set the atmel AT86RF233 pins to the default operating values: pin 11 ( slp_tr ) = l , pin 8 ( /rst ) = h and pin 23 ( /sel ) = h . all interrupts are disabled by default. th us, interrupts for state transition control are to be enabled first, for example enable irq_4 (awake_end) to indicate a state transition to trx_off state or interrupt irq_0 ( pll_lock ) to signal a locked pll in pll_on state . in p_on state a first access to the radio transceiver registers is possible afte r a default 1 mhz master clock is provided at pin 17 (clkm) , refer to t tr1 to table 7 - 1 . once the supply voltage has stabilized and the crystal oscillator has settled (see parameter t xtal refer to table 7 - 2 ), a valid spi write access to re gister bits trx_cmd ( register 0x 02 , trx_state) with the command trx_off or force_trx_off initiate a state change from p_on towards trx_off state , which is then indicated by an interrupt irq_4 (awake_end) if enabled . 7.1.2.2 sleep C sleep state in sleep state, the entire radio transceiver is disabled. no circuitry is operating beyond the circuitry monitoring pin 11 (slp_tr) and pin 8 (/rst) . this state can only be entered from state trx_off, by setting the slp_tr = h. if clkm is enabled with a clock rates higher than 250 khz , the sleep state is entered 35 clkm cycles after the rising edge at pin 11 (slp_tr) . at that time clkm is turned off . if the clk m output is already turned off ( register bits clkm_ctrl = 0 ), the sleep state is entered immediately. at clock rates 250 khz and 62.5 khz , the main clock at pin 17 ( clkm ) is turned off immediately. setting slp_tr = l returns the radio transceiver to the trx_ off state. during sleep state the radio transceiver register contents and the aes register contents remain valid while the content s of the frame buffer are destroyed . /rst = l in sleep state return s the radio transceiver to trx_off state and thereby sets all registers to their default values. exceptions are register bits clkm_ctrl ( register 0x 03, trx_ctrl_0). these register bits require a specific tr eatment, for details see section 9.6.4 . 7.1.2.3 prep_deep_sleep C deep sleep preparation state the state prep_deep_sleep is the preparation state for deep_s leep state. the state can be reached by writing the command prep_deep_sleep to register bits trx_cmd (register 0x02, trx_state). if clkm is enabled with a clock rates higher than 250 khz , the deep_sleep state is entered 35 clkm cycles after the rising edge at pin 11 (slp_tr). at that time clkm is turned off. if the clkm output is already turned off (register bits clkm_ctrl = 0), the
34 8351b C C AT86RF233 deep_sleep state is entered immediately. at clock rates 250 khz and 62.5 khz , the main clock at pin 17 (clkm) is turned off immediately. 7.1.2.4 deep_sleep C deep sleep state in deep_sleep state, the entire radio transceiver is disabled. no circu itry is operating beyond the circuitry monitoring pin 11 (slp_tr). the radio transceiver current consumption is reduced to leakage current only. this state can only be entered from state prep_dee p_sleep, by setting the slp_tr = h. setting slp_tr = l return s the radio transceiver to the trx_off state. after deep_sleep state the radio transceiver register contents and the aes register contents obtain the reset values while the contents of the frame buffer are destroyed. the clkm starts with the default 1 mhz master clock at pin 17 (clkm) after the crystal oscillator has stabilized. all digital inputs are pulled - up or pulled - down during deep_sleep state, refer to section 1.3.2 , except slp_tr. 7.1.2.5 trx_off C clock state in trx_off the crystal oscillator is running and the master clock is available if enabled. the spi interface and digital voltage regulator are enabled , thus the radio transceiver registers, the frame buffer and security engine (aes) are accessible (see section 9.3 and section 11.1 ). in contrast to p_on state the pull - up and pull - down configuration is disabled. p in 11 (slp_tr) and pin 8 ( /rst ) are available for state control. t he analog front - end is disabled during trx_off state . entering the trx_off state from p_on, sleep, deep_sleep or reset st ate is indicated by interrupt irq_4 (awake_end) if enabled . 7.1.2.6 pll_on C pl l state entering the pll_on state from trx_off state enables the analog voltage regulator (avreg) first. after the voltage regulator has been settled, the pll frequency synthesizer is enabled. when the pll has been settled at the receive frequency to a channel defined by register bits channel ( register 0x 08 , phy_cc_cca ) or register bits cc_number (register 0x13, cc_ctrl_0 ) and cc_band (register 0x14, cc_ctrl_1 ), refer to section 9.7.2 , a successful pll lock is indicated by issuing an interru pt irq_0 ( pll_lock ) . if an rx_on command is issued in pll_on state, the receiver is enabled immediately . if the pll has not been settled before the state ch ange nevertheless takes place . even if the register bits trx_status ( register 0x 01, trx_status) indicates rx_on , actual frame reception can only start once the pll has locked. the pll_on state corresponds to the tx_on state in ieee 802.15.4. 7.1.2.7 rx_on and busy_rx C rx listen and receive state in rx_on state the receiver is in the rx data polling mode and the pll frequency synthesizer is locked to its preprogrammed frequency. the atmel AT86RF233 receive mo de is internally separated into rx_on state and busy_rx state. there is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on. in both state s , the receiver and the pll fre quency synthesizer ar e enabled.
35 8351b C C AT86RF233 during rx_on state , the receiver listens for incoming frames . after d etect ing a valid synchronization header ( shr ) , the atmel AT86RF233 automatically enters the busy_rx state . the reception of a valid phy header ( p hr) generates an irq_2 ( rx_start ) and starts the psdu data demodulat ion . during psdu reception , the fr ame data are stored continuously in the frame buffer until the last byte was received. the completion of the frame reception is indicated by an interrupt irq_3 ( trx_end ) and the radio transceiver reenters the state rx_on. at the same time the register bit rx_crc_valid ( register 0x 06 , phy_rssi ) is updated with the result of the fcs check (see section 8.2 ). r eceive d frames are passed to the frame filtering unit , refer to section 7.2.3.4 . i f the content of the mac addressing fields (refer to [ 2 ] ieee 802.15.4 - 2006 section 7.2.1) of a frame matches to t he expected addresses, which is further depend ent on the addressing mode, an address match interrupt irq_5 ( ami ) is issued, refer to section 6.7 . the expected address values are to be stored in registers 0x20 C 0x2b (short address , pan - id and ieee address) . frame filtering is available in basic operating mode and extended operating mode , refer to section 7.2.3.4 . leaving state rx_on is possible by writing a state change command to register bits trx_cmd in register 0x 02 (trx_state). 7.1.2.8 busy_tx C transmit state in the busy_tx state AT86RF233 is in the data transmission state. a transmission can only be initiated from the pll_on state. the transmission can be started either by driving event such as: ? a r ising edge o n pin 11 (slp_tr) , or ? a serial tx_start command via the spi to register bits trx_cmd (register 0x02, trx_state ). either of these takes the radio transceiver into the busy_tx state. during the transition to the busy_tx state, the pll frequency shifts to the transmit frequency. t he actual t ransmission of the first data chip of the shr starts after 16 s to allow pll settling and pa ramp - up , see figure 7 - 7 . after transmission of the shr , the frame buffer content is transmitted. in case the phr indicate s a frame length of zero, the transmission is aborted immediately after the phr field. after the frame transmission has been completed, the AT86RF233 automatically turns off the power amplifier , generates an irq_3 ( trx_end ) interrupt and returns in to pll_on state. 7.1.2.9 reset state the reset state is to reset all registers and state machines of the at86rf 233 to their default values , e xception are register bits clkm_ctrl ( register 0x 03, trx_ctrl_0 ). th ese register bits require a specific treatment, for details see section 9.6.4 . a reset force s the radio transceiver into trx_off state. if the device is still in the p_on state it remains in the p_on state though. a reset is initiated with pin 8 ( /rst ) = l an d the state is left after setting /rst = h. the reset pulse should have a minimum length as specified in section 12.4 see parameter t 10 . during reset, the microcontroller has to set the radio transceiver control pins slp_tr and /se l to their default values. an overview about the register reset values is provided in table 14 - 2 .
36 8351b C C AT86RF233 7.1.3 interrupt handling all interrupts provided by the at mel AT86RF233 (see table 6 - 10 ) are supported in basic operating mode. for example, interrupts are provided to observe the status of radio tr ansceiver rx and tx operations. when being in receive mode, irq_2 ( rx_start ) indicates the detection of a valid phr first, irq_5 ( ami ) an address ma tch, and irq_3 ( trx_end ) the completion of the frame reception. during transmission, irq_3 ( trx_end ) indicates the completion of the fram e transmission. figure 7 - 2 shows a n example for a transmit/ receive transaction between two devices and the related interrupt events in basic operating mode. device 1 transmits a frame containing a mac header (in this example of length seven ), payload and valid fcs. the frame is received by device 2 which generates the interrupts during the processing of the incoming frame. the received frame is stored in the frame buffer. the first interrupt irq_2 ( rx_start ) signals the reception of a valid phr. if the received frame passes the address filter, refer to section 7.2.3.4 , an address match interrupt irq_5 ( ami ) is issued after the rec eption of the mac header (mhr). in basic operating mode the third interrupt irq_3 ( trx_end ) is issued at the end of the received frame. in extended operating mode, refer to section 7.2 ; the interrupt is only issued if the received frame passes the address filter and the fcs is valid. further exceptions are explained in section 7.2 . processing delay t irq is a typical value, refer to section 12.4 . figure 7 - 2 . timing of rx_start, ami and trx_end interrupts in basic operating mode . 128 160 192 0 192 +( 9 + m )* 32 - 16 time [ s ] r x ( d e v i c e 2 ) irq _ 2 ( rx _ start ) t irq rx _ on rx _ on irq trx _ state interrupt latency trx _ end irq _ 5 ( ami ) t irq t irq busy _ rx irq _ 3 ( trx _ end ) t x ( d e v i c e 1 ) pll _ on busy _ tx pll _ on irq slp _ tr trx _ state typ . processing delay f r a m e o n a i r preamble sfd phr msdu 4 1 1 m number of octets frame content mhr 7 fcs 2 t tr 10
37 8351b C C AT86RF233 7.1.4 basic operating mode timing this section depict s atmel AT86RF233 state transition s and their timing properties . timing figures are explained in table 7 - 1 , table 7 - 2 , and section 12.4 . 7.1.4.1 power - on procedure the power - on procedure to p_on state is shown in figure 7 - 3 . figure 7 - 3 . power - o n procedure to p_on state . when the external supply voltage (v dd ) is initially supplied to the AT86RF233 , the radio transceiver enables the crystal oscillator ( xosc ) and the internal 1.8v voltage regulator for the digital domain (dvreg). after t tr1 = 330 s (typ.), the master clock signal is available at pin 17 (clkm) at default rate of 1 mhz . as soon as clkm is available the spi is enabled and can be used to control the transceiver . as long as no state change towards state trx_off is performed , the radio transceiver remains in p_on state. 7.1.4.2 wake - up procedure from sleep the wake - up procedure from sleep state is shown in figure 7 - 4 . figure 7 - 4 . wake - up procedure from sleep state . t he radio transceiver s sleep state is left by releasing pin 1 1 ( slp_tr ) to logic low . this restarts the xosc and dvreg. after t tr2 = 210 s (typ.) the radio transceiver enters trx_off state. the internal clock signal is available and provided to pin 17 (clkm), if enabled. this procedure is similar to the power - o n procedure . however the radio transceiver automatically proceeds to the trx_off state. during thi s, transition the filter - tuning network (ftn) calibration is performed. entering trx_off state is signaled by 0 event state v dd on p _ on block xosc , dvreg 100 clkm on 400 time [ s ] time t tr 1 0 e v e n t s t a t e b l o c k c l k m o n t i m e [ s ] t i m e t t r 2 t r x _ o f f i r q _ 4 ( a w a k e _ e n d ) s l p _ t r = l s l e e p x o s c , d v r e g x o s c , d v r e g f t n 2 0 0
38 8351b C C AT86RF233 irq_4 (awake_end) , if this interrupt was enabled by the appropriate mask register bit . 7.1.4.3 wake - up procedure from deep_sleep the wake - up procedure from deep_sleep state is shown in figure 7 - 5 . figure 7 - 5 . wake - up procedure from deep_sleep state . the atmel AT86RF233 radio transceivers deep_sleep state is left by releasing slp_tr pin to logic low. this restarts the xosc and dvreg. after t tr18 = 360 s (typ.) the radio transceiver enters trx_off state. the internal clock signal is available and provided default rate of 1 mhz clock to pin 17 (clkm) . this procedure is similar to the power - on procedure. however the radio transceiver automatically proceeds to the trx_off state. during this, transition the filter - tuning network (ftn) calibration is performed. 7.1.4.4 pll_on and rx_on states the transition from trx_off to pll_on or rx_on mode is shown in figure 7 - 6 . figure 7 - 6 . transition from trx_off to pll_on or rx_on s tate . note s : 1. if trx_cmd = rx_on in trx_off state rx_on state is entered immediately, even if the pll has not settled. 2. timing figures t tr4 and t tr8 refers to table 7 - 1 . in trx_off state, entering the commands pll_on or rx_on initiates a ramp - up sequence of the internal 1.8v voltage regulator for the analog domain ( a vreg). rx_on state can be entered any time from pll_on state , regardless whether the pll has already locked, which is indicated by irq_0 ( pll_lock ) . 0 e v e n t s t a t e b l o c k c l k m o n t i m e [ s ] t i m e t t r 1 8 t r x _ o f f i r q _ 4 ( a w a k e _ e n d ) s l p _ t r = l d e e p _ s l e e p x o s c , d v r e g x o s c , d v r e g f t n 3 5 0 0 e v e n t s t a t e b l o c k 8 0 t i m e [ s ] t i m e t t r 4 i r q _ 0 ( p l l _ l o c k ) t r x _ o f f a v r e g c o m m a n d p l l _ o n p l l r x p l l _ o n r x _ o n t t r 8 r x _ o n
39 8351b C C AT86RF233 7.1.4.5 busy_tx and rx_on states the transition from pll_on to busy_tx state and subsequent ly to rx_on state is shown in figure 7 - 7 . figure 7 - 7 . pll _on to busy_ tx to rx_on timing . starting from pll_on state it is further assumed that the pll is already locked. a transmission is initiated either by a rising edge of pin 11 (slp_tr) or by command tx_ start , the atmel AT86RF233 changes into b usy_tx state . the pll settles to the transmit frequency and the pa is enabled. t tr10 = 16 s afte r initiating the transmission starts the internally generated shr transmission . after that the psdu data are transmitted from the frame buffer. after completing the frame transmi ssion , indicated by irq_3 ( trx_end ) , the pll settles back to the receive frequency within t tr11 = 32 s in s tate pll_on . if during tx_busy the radio transmitter is programmed to change to a receive state it automatically proceeds the state change to rx_on state after finishing the transmission . 7.1.4.6 reset procedure the radio transceiver reset procedure is shown in figure 7 - 8 . figure 7 - 8 . reset procedure . note: 1. timing figure t tr13 refers to table 7 - 1 , t 10 , t 11 refers to section 12.4 . time [ s ] 0 x 16 x + 32 time t tr 11 t tr 10 command rx _ on state block pll _ on rx _ on busy _ tx pin slp _ tr pa pll pa , tx rx pll or command tx _ start x e v e n t s t a t e b l o c k t i m e [ s ] p i n / r s t t r x _ o f f x + 3 0 [ i r q _ 4 ( a w a k e _ e n d ) ] 0 v a r i o u s t i m e > t 1 0 t t r 1 3 > t 1 1 x o s c , d v r e g x o s c , d v r e g x + 1 0 f t n
40 8351b C C AT86RF233 /rst = l sets all registers to their default values. exceptions are register bits clkm_ctrl ( register 0x 03, trx_ctrl_0), refer to section 9.6.4 . after releasing the reset pin 8 (/rst ) = h the wake - up sequence including an ftn calibration cycle is performed , refer to section 9.8 . after that the trx_off state is entered . figure 7 - 8 illustrates the reset procedure o nce the p_on state was left and the radio transceiver was not in sleep or deep_sleep state . the reset procedure is identical for all originating radio transceiver states except of state p_on, sleep, or deep_sleep . instead, here the procedure described in section 7.1.2.1 must be followed to enter the trx_off state . if the radio transceiver was in state sleep or deep_sleep , the xosc and dvreg are enab led before entering trx_off state. if register bits trx_status indicates state_transition_in_progress during system initialization until the atmel AT86RF233 reaches trx_off state , do not try to initiate a further state change while the radio transceiver is in this state. note s : 2. the reset impulse should have a minimum length t 10 = 625 ns as specified in section 12.4 . 3. an access to the device should not occur earlier than t 11 625 ns after releasing the /rst pin ; refer to section 12.4 . 4. a reset overrides an spi command request that might have be en queued.
41 8351b C C AT86RF233 7.1.4.7 state transition timing summary the atmel AT86RF233 transition numbers correspond to figure 7 - 1 and do not include spi access time unless otherwise stated. see measurement setup in figure 5 - 1 . table 7 - 1 . state transition timing . symbol parameter condition min. typ. max. unit t tr1 p_on ? clkm is available depends on crystal oscillator setup (c l = 10pf) and external capacitor at dvdd (100nf nom.). 330 1000 s t tr1a sleep ? clkm is available depends on crystal oscillator setup (c l = 10pf) and external capacitor at dvdd (100nf nom.). 180 1000 s t tr1b deep_sleep ? clkm is available depends on crystal oscillator setup (c l = 10pf) and external capacitor at dvdd (100nf nom.). 330 1000 s t tr2 sleep ? trx_off depends on crystal oscillator setup (c l = 10pf) and external capacitor at dvdd (100nf nom.). 210 1000 s t tr3 trx_off ? sleep for f clkm > 250khz. 35 clkm cycles otherwise. 0 clkm cycles t tr4 trx_off ? pll_on depends on external capacitor at avdd (100nf nom.). 80 s t tr5 pll_on ? trx_off 1 s t tr6 trx_off ? rx_on depends on external capacitor at avdd (100nf nom.). 80 s t tr7 rx_on ? trx_off 1 s t tr8 pll_on ? rx_on 1 s t tr9 rx_on ? pll_on transition time is also valid for tx_aret_on, rx_aack_on. 1 s t tr10 pll_on ? busy_tx when asserting pin 11 (slp_tr) or trx_cmd = tx_start first symbol transmission is delayed by one symbol period (pll settling and pa ramp - up). 16 s t tr11 busy_tx ? pll_on pll settling time. 32 s t tr12 various states ? trx_off using trx_cmd = force_trx_off; not valid for sleep or deep_sleep. 1 s t tr13 reset ? trx_off not valid for p_on, sleep, or deep_sleep. 26 s t tr14 various states ? pll_on using trx_cmd = force_pll_on; not valid for p_on, sleep, deep_sleep, or reset. 1 s t tr15 p_on ? trx_off using trx_cmd = trx_off directly after clkm is available. 360 1000 s t tr16 prep_deep_sleep ? trx_off 1 s t tr17 trx_off ? prep_deep_sleep 1 s
42 8351b C C AT86RF233 symbol parameter condition min. typ. max. unit t tr18 deep_sleep ? trx_off depends on crystal oscillator setup (c l = 10pf) and external capacitor at dvdd (100nf nom.). 360 1000 s t tr19 prep_deep_sleep ? deep_sleep for f clkm > 250khz. 35 clkm cycles otherwise. 0 clkm cycles the state transition timing is calculated based on the timing of the individual blocks shown in figure 7 - 3 to figure 7 - 8 . the worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations. table 7 - 2 . b lock initialization and settling time . symbol parameter condition min. typ. max. unit t xtal reference oscillator settling time start xtal ? clock available at pin 17 (clkm). depends on crystal q factor and load capacitor. 330 1000 s t ftn ftn calibration time 25 s t dvreg dvreg settling time depends on external bypass capacitor at dvdd (cb3 = 100nf nom., 10f worst case). 50 1000 s t avreg avreg settling time depends on external bypass capacitor at avdd (cb1 = 100nf nom., 10f worst case). 50 1000 s t pll_init initial pll settling time pll settling time trx_off ? pll_on, including 40s avreg settling time. 80 250 s t pll_sw pll settling time on channel switch duration of channel switch within frequency band. 11 100 s t pll_cf pll cf calibration pll center frequency calibration. 8 8 24 s t pll_dcu pll dcu calibration pll dcu calibration. 6 6 s t rx_tx rx ? tx maximum settling time rx ? tx. 16 s t tx_rx tx ? rx maximum settling time tx ? rx. 32 s t shr_sync shr, sync shr synchronization period. 32 96 160 s t rssi rssi, update rssi update period in receive states. 2 s t ed ed measurement ed measurement period is eight symbols. 135 180 s t cca cca measurement cca measurement period is eight symbols. 135 180 s t rnd random value, update random value update period. 1 s t aes aes core cycle time 23.4 24 s
43 8351b C C AT86RF233 7.1.5 register description register 0x01 (trx_status): the read - only register trx_status signals the present state of the radio transceiver as well as the status of a cca operation. figure 7 - 9 . register trx_status. bit 7 6 5 4 0x01 cca_done cca_status reserved trx_status trx_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x01 trx_status trx_status read/write r r r r reset value 0 0 0 0 ? bit 4:0 - trx_status the register bits trx_status signal the current radio transceiver status. table 7 - 3 . trx_status. register bits value description trx_status 0x00 p_on 0x01 busy_rx 0x02 busy_tx 0x06 rx_on 0x08 trx_off (clk mode) 0x09 pll_on (tx_on) 0x0f (1) sleep 0x10 prep_deep_sleep 0x11 (2) busy_rx_aack 0x12 (2) busy_tx_aret 0x16 (2) rx_aack_on 0x19 (2) tx_aret_on 0x1f (3) state_transition_in_progress all other values are reserved notes: 1. in sleep or deep_sleep state register not accessible. 2. extended operating mode only. 3. do not try to initiate a further state change while the radio transceiver is in state_transition_in_progress state. a read access to register bits trx_status reflects the current radio transceiver state. a state change is initiated by writing a state transition command to register bits trx_cmd (register 0x02, trx_state). alternatively , some state transition s can be initiated by the rising edge of pin 11 (slp_tr) in the appropriate state. these register bits are used for basic and extended operating mode, see section 7.2 . if the requested state transition has not be en completed, the trx_status returns state_transition_in_progress value . do not try to initiate a further state
44 8351b C C AT86RF233 change while the radio transceiver is in state_transition_in_progress state . state transition timings are defined in table 7 - 1 . register 0x02 (trx_state): the radio transceiver states are controlled via register trx_state using register bits trx_cmd. the read - only register bits trac_status indicate the status or result of an extended operating mode transaction. figure 7 - 10 . register trx_state. bit 7 6 5 4 0x02 trac_status trx_cmd trx_state read/write r r r r/w reset value 0 0 0 0 bit 3 2 1 0 0x02 trx_cmd trx_state read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 4:0 - trx_cmd a write access to register bits trx_cmd initiate a radio transceiver state transition to the new state. table 7 - 4 . trx_cmd. register bits value description trx_cmd 0x00 (1) nop 0x02 (2) tx_start 0x03 force_trx_off 0x04 (3) force_pll_on 0x06 rx_on 0x08 trx_off (clk mode) 0x09 pll_on (tx_on) 0x10 prep_deep_sleep 0x16 (4) rx_aack_on 0x19 (4) tx_aret_on all other values are reserved notes: 1. trx_cmd = D0 after power on reset (por). 2. the frame transmission starts one symbol after tx_start command. 3. force_pll_on is not valid for states p_on, sleep, deep_sleep, and reset, as well as state_transition_in_progress towards these states. 4. extended operating mode only. a write access to register bits trx_cmd initiate s a radio transceiver state t ransition towards the new state. these register bits are used for basic and extended operating mode, see section 7.2 .
45 8351b C C AT86RF233 7.2 extended operating mode e xtended operating mode makes up for a large set of automated functionality add - ons which can be referred to a s a hardware mac accelerator . these add - ons go beyond the basic radio transceiver functionality provided by the basic operating mode . extended operating mode functions handle time critical mac tasks, requested by the ieee 802.15.4 standard , in hardware , such as automatic acknowledgement, automatic csma - ca, and retransmission. this results in a more efficient ieee 802.15.4 software mac im plementation, including reduced code size, and may allow use of a smaller microcontroller or operation at low clock rates. the extended operating mode is designed to support ieee 802.15.4 - 2006 and ieee 802.15.4 - 20 11 compliant frames; the mode is backward c ompatible to ieee 802.15.4 - 2003 and supports non ieee 802.15.4 compliant frames. this m ode comprises the following procedures : auto matic acknowledgement (rx_aack) divides into the tasks : ? frame reception and automatic fcs check ? configurable addressing fiel d s check ? interrupt indicating address match ? interrupt indicating frame reception, if it passes address filtering and fcs check ? automatic ack frame transmission (if the received frame passed the address filter and fcs check and if an ack is required by the frame type and ack request) ? support of slotted acknowledgment using slp_tr pin (used for beacon - enabled operation) automatic csma - ca and retransmission ( tx_aret ) divides into the tasks : ? csma - ca , including automatic cca retry and random backoff ? frame transmission and automatic fcs field generation ? reception of ack frame (if an ack was requested) ? automatic retry of transmissions if ack was expected but not received or accepted ? interrupt signaling with transaction status automatic fcs check and ge neration , refer to section 8.2 , is used by the rx_aack and tx_aret modes . in rx_aack mode , an automatic fcs check is always performed for incoming frames. in tx_aret mode , an ack , received within the time required by ieee 802.15.4, is accepted if the fcs is valid, and if the sequence number of the ack matches the sequence number of the previously transmitted frame. depend ent o n th e value of the frame pending subfield in the received acknowledgement frame the transaction status is set , see trac_status , section 7.2.7 . a n atmel AT86RF233 state diagram , including the extended operating mode states is shown in figure 7 - 11 . orange marked states represent the basic operating mode; blue marked states represent the extended operating mode.
46 8351b C C AT86RF233 figure 7 - 11 . extended operating mode state diagram . l e g e n d : b l u e : s p i w r i t e t o r e g i s t e r t r x _ s t a t e ( 0 x 0 2 ) r e d : c o n t r o l s i g n a l s v i a i c p i n g r e e n : e v e n t b a s i c o p e r a t i n g m o d e s t a t e s e x t e n d e d o p e r a t i n g m o d e s t a t e s p l l _ o n r x _ o n p l l _ o n t r x _ o f f ( c l o c k s t a t e ) x o s c = o n p u l l = o f f r x _ o n ( a l l m o d e s e x c e p t p _ o n ) f o r c e _ t r x _ o f f ( a l l m o d e s e x c e p t s l e e p o r d e e p _ s l e e p ) f r a m e e n d r x _ o n ( r x l i s t e n s t a t e ) b u s y _ r x ( r e c e i v e s t a t e ) t r x _ o f f t r x _ o f f 4 5 7 6 8 9 b u s y _ r x _ a a c k b u s y _ t x _ a r e t s h r d e t e c t e d t r a n s - a c t i o n f i n i s h e d t x _ a r e t _ o n p l l _ o n s l p _ t r = h o r t x _ s t a r t f r a m e e n d p l l _ o n r x _ a a c k _ o n t x _ a r e t _ o n r x _ a a c k _ o n f r o m / t o t r x _ o f f f r o m / t o t r x _ o f f / r s t = h 1 2 1 3 f o r c e _ p l l _ o n 1 4 s h r d e t e c t e d t x _ a r e t _ o n r x _ a a c k _ o n p l l _ o n ( p l l s t a t e ) s e e n o t e s r e s e t ( f r o m a l l s t a t e s ) / r s t = l t r x _ o f f t r x _ o f f 2 t r x _ o f f s l p _ t r = h 3 p _ o n ( p o w e r - o n a f t e r v d d ) x o s c = o n p u l l = o n s l e e p ( s l e e p s t a t e ) x o s c = o f f p u l l = o f f s l p _ t r = l d e e p _ s l e e p ( s l e e p s t a t e ) x o s c = o f f p u l l = o n r x _ a a c k _ o n t x _ a r e t _ o n r x _ a a c k _ o n r x _ o n t x _ a r e t _ o n r x _ o n x o s c = o n p u l l = o f f p r e p _ d e e p _ s l e e p ( p r e p a r e s l e e p s t a t e ) t r x _ o f f p r e p _ d e e p _ s l e e p f r a m e e n d b u s y _ t x ( t r a n s m i t s t a t e ) t x _ s t a r t o r 1 1 1 0 s l p _ t r = h 1 5 1 6 1 7 s l p _ t r = h s l p _ t r = l 1 8 1 9
47 8351b C C AT86RF233 7.2.1 state control the extended operating mode include rx_aack and tx_aret modes and are controlled by writing respective command to register bits trx_cmd (register 0x02, trx_state ) . the corresponding states, rx_aack_on and tx_aret_on respectively, are to be entered from states trx_off or pll_on as illustrated by figure 7 - 11 . the completion of each state change command shall always be confirmed by reading the register bits trx_status (register 0x01, trx_status) . rx_aack - receive with automatic acknowledgement a state transition to rx_aack_on is initiated by writing the command rx_aack_on to the register bits trx_cmd. the state change should be confirmed by reading register bits trx_status (register 0x01, trx_status). the rx_aack extended operating mode is left by writing a new command to the register bits trx_cmd. if the at mel AT86RF233 is within a frame receive or acknowledgment procedure (busy_rx_aack) , the state change is executed after finish ing . alternatively, the commands force_trx_off or force_pll_on can be used to cancel the rx_aack transaction and change into radio transceiver state trx_off or pll_on, respectively. tx_aret - transmit with automatic frame retransmission and csma - ca retry a state transition to tx_aret_on is initiated by writing command tx_aret_on to register bits trx_cmd (register 0x02, trx_state) . the radio transceiver is in the tx_aret_on state after register bits trx_status (register 0x01, trx_status) changes to tx_aret_on. the tx_aret transaction is started with a rising edge of pin 11 (slp_tr) or writing the command tx_start to register bits trx_cmd. the tx_aret extended operating mode is left by writing a new command to the register bits trx_cmd. if the AT86RF233 is within a csma - ca transaction, a frame transmission or an acknowledgment procedure (busy_tx_aret) , the state change is executed after finish ing . alternatively , the command force_trx_off or force_pll_on can be used to instantly terminate the tx_aret transaction and change into radio transceiver state trx_of f or pll_on, respectively. note: 1. a state change request from trx_off to rx_aack_on or tx_aret_on internally passes the state pll_on to initiate the radio transceiver front end. thus, the readiness to receive or transmit data is delayed accordingly (see table 7 - 1 ). in that case, it is recommended to use interrupt irq_0 ( pll_lock ) as an indicator.
48 8351b C C AT86RF233 7.2.2 configuration as the usage of the extended operating mode is based on basic operating mode functionality, only features beyond the basic radio transceiver functionality are described in the following sections. for details of the basic operating mode, refer to section 7.1 . when using the rx_aack or tx_aret modes, the following registers needs to be configured. rx_aack configuration steps: ? short address, pan - id and ieee address registers 0x20 C 0x2b ? configure rx_aack properties register s 0x2c, 0x2e o handling of frame version subfield o handling of pending data i ndicator o characterize as pan coordinator o handling of slotted acknowledgement ? additional frame filtering pro perties register s 0x17 , 0x2e o promiscuous mode o enable or disable automatic ack generation o handling of reserved frame types the addresses for the address match algorithm are to be stored in the appropriate address registers. additional control of the rx_aa ck mode is done with register 0x 17 (xah_ctrl_1) and register 0x 2e (csma_seed_1). as long as a short address has not been set, only broadcast frames and frames matching the ieee address can be received. configuration examples for different device operating modes and handling of various frame types can be found in section 7.2.3.1 . tx_aret configuration steps: ? leave register bit tx_auto_crc_on = 1 register 0x 04, trx_ctrl_1 ? configure csma - ca o max_frame_retries register 0x 2c, xah_ctrl_0 o max_csma_retries register 0x 2c, xah_ctrl_0 o csma_seed registers 0x2d, 0x2e o max_be, min_be register 0x 2f, csma_be ? configure cca (see section 8.5 ) max_frame_retries ( register 0x 2c , xah_ctrl_0 ) defines the maximum number of frame retransmissions. the register bits max_csma_retries ( register 0x 2c , xah_ctrl_0 ) co nfigure the number of csma - ca retries af ter a busy channel is detected. the register bits csma_seed (registers 0x2d, 0x2e) define a random seed for the backoff - time random - number generator in the atmel AT86RF233 . the register bits max_be and min_be ( register 0x 2f , csma_be ) set the maximum and minimum csma backoff exponent ( see [ 2 ] ) , respectively .
49 8351b C C AT86RF233 7.2.3 rx_aack_on C receive with automatic ack the rx_ aack extended operating mode handles reception and automatic acknowledgement of ieee 802.15.4 compliant frames. the general functionality of the rx_aack procedure is shown in figure 7 - 12 . the gray shaded area is the standard flow of an rx_aack transaction for ieee 802.15.4 compliant frames, refer to section 7.2.3.2 . all other procedures are exceptions for specific operating modes or frame formats, refer to section 7.2.3.3 . in rx_ aack_on state, the atmel AT86RF233 listens for incoming frames. after detecting a valid phr, the radio transceiver changes into busy_rx_aack state and parses the frame content of the mac header (mhr) , refer to section 8 .1.2 . if the content of the mac addressing fields of the received frame (refer to ieee 802.15.4 section 7.2.1 ) matches one of the configur ed addresses, dependent on the addressing mode, an address match interrupt irq_5 ( ami ) is issued, refer to section 7.2.3.4 . the reference address values are to be stored in registers 0x20 C 0x2b (short address, pan - id and ieee address). frame filtering as described in section 7.2.3.4 is also applied in basic operating mode. however, in basic operating mode, the result of frame filtering or fcs check do not affect the generation of an interrupt irq_3 ( trx_end ) . generally, at nodes configured as a normal device or pan coordinator, a frame is indicated by interrupt irq_3 ( trx_end ) if the frame passes the frame filter and the fcs is valid. the interrupt is issued after the completion of the frame reception. the microcontroller can then read the frame data. an exception ap plies if promiscuous mode is enabled, see section 7.2.3.2 . in that case, an interrupt irq_3 ( trx_end ) is issued for all frames. during reception the AT86RF233 parses bit [5] (ack request) of the frame control field of the received data or mac command frame to check if an acknowledgement (ack) reply is expected. if the bit is set and if the frame passes the third level of filtering, see ieee 802.15.4 - 2006, section 7.5.6.2 , the radio transceiver automatically generates and transmits an ack frame. the sequence number is copie d from the received frame. the content of the frame pending subfield of the ack response is set by register bit aack_set_pd ( register 0x 2e, csma_seed_1) when the ack frame is sent in response to a data request mac command frame , other wise this subfield is set to zero . by default, the acknowledgment frame is transmitted aturnaroundtime ( 12 symbol periods ; see ieee 802.15.4 - 2006 , section 6.4.1 ) after the reception of the last symbol of a data or mac command frame. optionally, for non - compliant networks, this delay can be reduced to two symbols by register bit aack_ack_time (register 0x2e, xah_ctrl_1). if the register bit aack_dis_ack ( register 0x 2e, csma_seed_1) is set, no acknowledgement frame is sent even if an acknowledgment frame was requested. this is useful for operating the mac hardware accelerator in promiscuous mode, see section 7.2.3.2 . for slotted operation, the start of the transmission of acknowledgement frames is controlled by pin 11 (slp_tr), refer to section 7.2.3.5 . the status of the rx_aack operation is indicated by register bits tr ac _status ( register 0x 0 2 , tr ac _status), see section 7.2.7 . during the operations described above , the AT86RF233 remains in busy_rx_aack state.
50 8351b C C AT86RF233 figure 7 - 12 . flow diagram of rx_aack . r e s e r v e d f r a m e s t r x _ s t a t e = r x _ a a c k _ o n s h r d e t e c t e d t r x _ s t a t e = b u s y _ r x _ a a c k s c a n n i n g m h r f r a m e r e c e p t i o n f r a m e f i l t e r i n g a c k r e q u e s t e d ( s e e n o t e 3 ) w a i t 1 2 s y m b o l p e r i o d s t r a n s m i t a c k t r x _ s t a t e = r x _ a a c k _ o n n y n y g e n e r a t e i r q _ 2 ( r x _ s t a r t ) a a c k _ p r o m _ m o d e = = 1 g e n e r a t e i r q _ 5 ( a m i ) y g e n e r a t e i r q _ 3 ( t r x _ e n d ) f r a m e r e c e p t i o n n o t e 3 : a d d i t i o n a l c o n d i t i o n s : - a c k r e q u e s t e d & - a a c k _ d i s _ a c k = = 0 & - f r a m e _ v e r s i o n < = a a c k _ f v n _ m o d e s l o t t e d o p e r a t i o n = = 0 y a a c k _ a c k _ t i m e = = 0 y w a i t 2 s y m b o l p e r i o d s p i n 1 1 ( s l p _ t r ) r i s i n g e d g e n n g e n e r a t e i r q _ 3 ( t r x _ e n d ) n y n w a i t 2 s y m b o l p e r i o d s f c s v a l i d ( s e e n o t e 2 ) y n a a c k _ u p l d _ r e s _ f t = = 1 f c s v a l i d g e n e r a t e i r q _ 3 ( t r x _ e n d ) y y n n n n o t e 2 : f c s c h e c k i s o m i t t e d f o r p r o m i s c o u s m o d e f c f [ 2 : 0 ] > 3 n y y p r o m i s c u o u s m o d e n o t e 1 : f r a m e f i l t e r i n g , p r o m i s c u o u s m o d e a n d r e s e r v e d f r a m e s : - a r a d i o t r a n s c e i v e r i n p r o m i s c u o u s m o d e , o r c o n f i g u r e d t o r e c e i v e r e s e r v e d f r a m e s h a n d l e s r e c e i v e d f r a m e s p a s s i n g t h e t h i r d l e v e l o f f i l t e r i n g - f o r d e t a i l s r e f e r t o t h e d e s c r i p t i o n o f p r o m i s c u o u s m o d e a n d r e s e r v e d f r a m e t y p e s ( s e e n o t e 1 )
51 8351b C C AT86RF233 7.2.3.1 description of rx_aack configuration bits overview rx_aack configuration as described below shall be done prior to switching the AT86RF233 into state rx_aack_on, refer to section 7.2.1 . table 7 - 5 s ummarizes all register bits which affect the behavior of an rx_aack transaction. for address filtering it is further required to setup address registers to match the expected address. a graphical representation of various operating modes is illustrated in figure 7 - 12 . table 7 - 5 . overview of rx_aack configuration bits . register address register bits register name description 0x20,0x21 0x22,0x23 0x24 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ieee_addr_7 set node addresses . 0x0c 7 rx_safe_mode protect buffer after frame re ception . 0x17 1 aack_prom_mode support promiscuous mode . 0x17 2 aack_ack_time change auto acknowledge start time . 0x17 4 aack_upl d _res_ft enable reserved frame type reception , needed to receive non - standard compliant frames . 0x17 5 aack_flt r _res_ft filter reserved frame types like data frame type, needed for filtering of non - standard compliant frames . 0x2c 0 slotted_operation if set, acknowledgment transmission has to be triggered by pin 11 (slp_tr) . 0x2e 3 aack_i_am_coord if set, the device is a pan coordinator, that is responds to a null address . 0x2e 4 aack_dis_ack disable generation of acknowledgment . 0x2e 5 aack_set_pd set frame pending subfield in frame c ontrol field (fcf), refer to section 8.1.2.2 . 0x2e 7:6 aack_fvn_mode controls the ack behavior , depend ing on fcf frame version number . the usage of the rx_aack configuration bits for v arious operati ng modes of a node is explained in the following section s . configuration bits not mentioned in the following two sections should be set to their reset values according to table 14 - 2 . all registers mentioned in table 7 - 5 are described in section 7.2.6 . the general behavior of the D atmel AT86RF233 extended feature set, chapter 11 , settings: o oqpsk_data_rate (psdu data rate) o oqp sk_scram_en (scrambler for 2 000k b/s data rate) o sfd_value (alternative sfd value) o ant_div (antenna d iversity) o rx_pdt_level (blocking frame reception of lower power signals) o rpc ( reduced power consumption )
52 8351b C C AT86RF233 are completely independent from rx_aack mode and can be arbitrarily combined . 7.2.3.2 configuration of ieee compliant scenarios device not operating as a pan coordinator table 7 - 6 shows a typical atmel AT86RF233 rx_aack configur ation of an ieee 802.15.4 device operating as a normal device, rather th an a pan coordinator or router . table 7 - 6 . configuration of ieee 802. 15.4 devices . register address register bits register name description 0x20,0x21 0x22,0x23 0x24 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ieee_addr_7 set node addresses . 0x0c 7 rx_safe_mode 0 : d isable frame protection . 1 : e nable frame protection . 0x2c 0 slotted_operation 0 : s lotted acknowledgment transmissions are not to be used . 1 : s lotted acknowledgment transmissions are to be used . 0x2e 7:6 aack_fvn_mode controls the ack behavior, depending on fcf frame version number . b 00 : a cknowledges only frames with version number 0, that is according to ieee 802.15.4 - 2003 frames . b 01 : a cknowledges only frames with version number 0 or 1, that is frames according to ieee 802.15.4 - 2006. b 10 : a cknowledges only frames with version number 0 or 1 or 2 . b 11 : a cknowledges all frames, independent of the fcf frame version number . notes: 1. the default value of the short address is 0xffff. thus, if no short address has been configured, only frames with either the broadcast address or the ieee address are accepted by the frame filter. 2. in the ieee 802.15.4 - 2003 standard the frame version subfield does not yet exist but is marked as reserved. according to this standard, reserved fields have to be set to zero. at the same time, the ieee 802.15.4 - 2003 standard requires ignoring reserved bits upon reception. thu s, there is a contradiction in the standard which can be interpreted in two ways: a. if a network should only allow access to nodes compliant to ieee 802.15.4 - 2003 , then aack_fvn_mode should be set to zero . b. if a device should acknowledge all frames independen t of its frame version, aack_fvn_mode should be set to three . however, this may result in conflicts with co - existing ieee 802.15.4 - 2006 standard compliant networks. the same holds for pan coordinators, see below.
53 8351b C C AT86RF233 pan - coordinator table 7 - 7 shows the atmel AT86RF233 rx_aack configuration for a pan coordinator. table 7 - 7 . configuration of a pan coordinator . register address register bits register name description 0x20,0x21 0x22,0x23 0x24 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ieee_addr_7 set node addresses . 0x0c 7 rx_safe_mode 0 : d isable frame protection . 1 : e nable frame protection . 0x2c 0 slotted_operation 0 : s lotted acknowledgment transmissions are not to be used . 1 : s lotted acknowledgment transmissions are to be used . 0x2e 3 aack_i_am_coord 1 : d evice is pan coordinator . 0x2e 5 aack_set_pd 0 : f rame pending subfield is not set in fcf . 1 : f rame pending subfield is set in fcf . 0x2e 7:6 aack_fvn_mode controls the ack behavior, depends on fcf frame version number . b 00 : a cknowledges only frames with version number 0, that is accordi ng to ieee 802.15.4 - 2003 frames. b 01 : a cknowledges only frames with version number 0 or 1, that is frames according to ieee 802.15.4 - 2006. b 10 : a cknowledges only frames with version number 0 or 1 or 2 . b 11 : a cknowledges all frames, independent of the fcf f rame version number. promiscuous mode the promiscuous mode is described in ieee 802.15.4 - 2006 , section 7.5.6.5 . this mode is further illustrated in figure 7 - 12 . according to ieee 802.15.4 - 2006 w hen in promiscuous mode, the mac sub layer shall pass received frames with correct fcs to the next higher layer and shall not process them further. that impl ies that received frames should never be automatically acknowledged. only second level filter rules as defined by ieee 802.15.4 - 2006, section 7.5.6.2, are applied to the received frame.
54 8351b C C AT86RF233 table 7 - 8 shows the typical configuration of a device operating in promiscuou s mode. table 7 - 8 . configuration of promiscuous mode . register address register bits register name description 0x20,0x21 0x22,0x23 0x24 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ieee_addr_7 each address shall be set: 0x00 . 0x17 1 aack_prom_mode 1 : enable promiscuous mode . 0x2e 4 aack_dis_ack 1 : disable generation of acknowledgment . 0x2e 7:6 aack_fvn_mode controls the ack behavior, depends on fcf frame version number . b 00 : a cknowledges only frames with version number 0, that is according to ieee 802.15.4 - 2003 frames . b 01 : a cknowledges only frames with version number 0 or 1, that is frames according to ieee 802.15.4 - 2006. b 10 : a cknowledges only frames with version number 0 or 1 or 2 . b 11 : a cknowledges all frames, independent of the fcf frame version number . if the atmel AT86RF233 radio transceiver is in promiscuous mode, second level of filtering according to ieee 802.15.4 - 2006, section 7.5.6.2, is applied to a received frame. however, an irq_3 ( trx_end ) is issued even if the fcs is invalid . thus, it is necessary to read register bit rx_crc_valid (register 0x06, phy_rssi) after irq_3 ( trx_end ) in order to verify the reception of a frame with a valid fcs. alternatively, bit[ 7 ] of byte rx_sta tus can be evaluated, refer to section 6.3.2 . if a device, operating in promiscuous mode, receives a frame with a valid fcs which further passed the third level of filtering according to ieee 802.15.4 - 2006, section 7.5.6.2, an acknowledgement (ack) f rame would be transmitted . but, according to the definition of the promiscuous mode, a received frame shall not be acknowledged, even if requested. thus, register bit aack_dis_ack (register 0x2e, csma_seed_1) must be set to one to disable ack generation. in all receive modes an irq_5 ( ami ) interrupt is issued, when the received frame matches the nodes address according to the filter rules described in section 7.2.3.4 . alternatively, in basic operating mode rx_on state , when a valid phr is detected, an irq_2 ( rx_start ) is generated and the frame is received. t he end of the frame reception is signalized with an irq_3 ( trx_end ) . at the same time the register bit rx_crc_valid ( register 0x 06, phy_rssi) is updated with the result of the fcs check (see section 8.2 ). according to the promiscuous mode definition the register bit rx_crc_valid needs to be checked in order to dismiss corrupted frames.
55 8351b C C AT86RF233 7.2.3.3 configuration of non ieee 802.15.4 compliant scenarios sniffer table 7 - 9 shows a n atmel AT86RF233 rx_aack configuration to setup a sniffer device. other rx_aack configuration bits, refer to table 7 - 5 , should be set to their reset values. all frames received are indicated by a n irq_2 ( rx_start ) and irq_3 ( trx_end ) . after frame reception register bit rx_crc_valid ( r egister 0x 06, phy_rssi) is updated with the result of the fcs check (see section 8.2 ). the rx_crc_valid bit needs to be checked in order to dismiss corrupted frames. table 7 - 9 . configuration of a sniffer device . register address register bits register name description 0x17 1 aack_prom_mode 1 : enable promiscuous mode . 0x2e 4 aack_dis_ack 1 : disable generation of acknowledgment . this operating mode is similar to the promiscuous mode. reception of reserved frames in rx_aack mode, frames with reserved frame types ( refer to section 8.1.2.2 ) can also be handled. this might be required when implementing proprietary, non - standard compliant, protocols . the reception of reserved frame types is an extension of t he AT86RF233 frame filter. received frames are either handled like data frames, or may be allowed to completely bypass the frame filter . the flow chart in figure 7 - 12 shows the corresponding state machine. the following table 7 - 10 shows rx_aack configu ration registers required to setup a node t o receive reserved frame types. table 7 - 10 . rx_aack configuration to receive reserved frame types . register address register bits register name description 0x20,0x21 0x22,0x23 0x24 0x2b short_addr_0/1 pan_addr_0/1 ieee_addr_0 ieee_addr_7 set node addresses . 0x0c 7 rx_safe_mode 0 : d isable frame protection . 1 : e nable frame protection . 0x17 4 aack_upld_res_ft 1 : enable reserved frame type reception . 0x17 5 aack_fltr_res_ft filter reserved frame types like data frame type, see note below . 0 : d isable reserved frame types filtering. 1 : enable reserved frame types filtering. 0x2c 0 slotted_operation 0 : s lotted acknowledgment transmissions are not to be used . 1 : s lotted acknowledgment transmissions are to be used .
56 8351b C C AT86RF233 register address register bits register name description 0x2e 3 aack_i_am_coord 0 : device is not pan coordinator. 1 : d evice is pan coordinator . 0x2e 4 aack_dis_ack 0 : enable generation of acknowledgment . 1 : disable generation of acknowledgment . 0x2e 7:6 aack_fvn_mode controls the ack behavior, depends on fcf frame version number . b 00 : a cknowledges only frames with version number 0, that is according to ieee 802.15.4 - 2003 frames . b 01 : a cknowledges only frames with version number 0 or 1, that is frames according to ieee 802.15.4 - 2006. b 10 : a cknowledges only frames with version number 0 or 1 or 2 . b 11 : a cknowledges all frames, independent of the fcf frame version nu mber. there are three different options for handling reserved frame types. 1. aack_upld_res_ ft = 1, aack_flt_res_ft = 0: any non - corrupted frame with a reserved frame type is indicated by an irq_3 ( trx_end ) interrupt. no further addre ss filtering is applied on those frames. an irq_5 ( ami ) interrupt is never generated and the acknowledgment subfield is ignored. 2. aack_upld_res_ft = 1, aack_flt_res_ft = 1: if aack_flt_res_ft = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. this implies the generation of the irq_5 ( ami ) interrupts upon address match. an irq_3 ( trx_end ) interrupt is only generated if the address matched and the frame was not corrupted. an acknowledgment is only send, when the ack request subfield was set in the received frame and an irq_3 ( trx_end ) interrupt occurred. 3. aack_upld_res_ft = 0: any received frame with a reserved frame type is discarded.
57 8351b C C AT86RF233 short acknowledgment frame ( ack) start timing register bit aack_ ack_time ( register 0x 17, xah_ctrl_1 ), see table 7 - 11 , defines the symbol time between frame reception and transmis sion of an acknowledgment frame . table 7 - 11 . overview of rx_aack configuration bits . register address register bit register name description 0x17 2 aack_ack_time 0 : ieee 802.15.4 s tandard compliant acknowledgement timing of 12 symbol periods. in slotted acknowledgement operation mode, the acknowledgment frame transmission can be triggered two symbol periods after reception of the frame earliest. 1 : non - s tandard ieee 802.15.4 r educed acknowledgment timing is set to 32 s ( two symbol periods ). t his feature can be used in all scenarios, independent of other configurations. however, shorter acknowledgment timing is especially useful when using high data rate modes to increase battery lifetime and to improve the overall data throughput; refer to section 11.3 . 7.2.3.4 frame filtering frame filter ing is an evaluation whether or not a received frame is addressed to this node. to accept a received frame and to generate an address match interrupt irq_5 ( ami ) a fil tering procedure as described in ieee 802.15.4 - 2006 section 7.5.6.2. ( third level of filtering ) is applied to the frame. the atmel AT86RF233 rx_aack mode accepts only frames that satisfy all of the following requirements (quote from ieee 802.15.4 - 2006 , section 7.5.6.2 ): 1. the frame type subfield shall not contain a reserved frame type. 2. the frame version subfield shall not contain a reserved value. 3. if a desti nation pan identifier is included in the frame, it shall match macpanid or shall be the broadcast pan identifier (0xffff ). 4. if a short destination address is included in the frame, it shall match either macshortaddress or the broadcast address (0xffff). oth erwise, if an extended destination address is included in the frame, it shall match aextendedaddress . 5. if the frame type indicates that the frame is a beacon frame, the source pan identifier shall match macpanid unless macpanid is equal to 0xffff, in which case the beacon frame shall be accepted regardless of the source pan identifier . 6. if only source addressing fields are included in a data or mac command frame, the frame shall be accepted only if the device is the pan coordinator and the source pan identifi er matches macpanid . moreover the AT86RF233 h as two additional requirements: 7. the frame type indicates that the frame is not an ack frame (refer to table 8 - 5 ). 8. at least one address field must be present.
58 8351b C C AT86RF233 address match, indicated by interrupt irq_5 ( ami ) , is f urther controlled by the content of subfields of the frame control field of a received frame according to the following rule: if (destination addressing mode = 0 or 1) and (source addressing mode = 0) no irq_5 ( ami ) is generated, refer to section 8.1.2.2 . this effectively causes all acknowledgement frames not to be announced, which would otherwise always pass the filter, regardless of whether they are intended for this device or not. for backward compatibility to ieee 802.15.4 - 2003 third level filter rule two (frame version) can be disabled by register bits aack_f vn_mode ( register 0x 2e, csma_seed_1). frame filtering is available in extended and basic operating mode , refer to section 7.1 , a frame passing the frame filtering generates an irq_5 ( ami ) , if enabled . notes: 1. filter rule one is affected by register bits aack_fltr_res_ft and aack_upld_res_ft, section 7.2.7 . 2. filter rule two is affected by register bits aack_fvn_mode, section 7.2.7 . 7.2.3.5 rx_aack slotted operation C slotted acknowledgement atmel AT86RF233 supports slotted acknowledgement operation, refer to ieee 802.15.4 - 2006, section 7.5.6.4.2 , in conjunction with the microcontroller. in rx_aack mode with register bit slotted_operation ( register 0x 2c, xah_ctrl_0) set, the transmission of a n acknowledgemen t frame has to be controlled by the microcontroller. if an ack frame has to be transmitted, the radio transceiver expects a rising edge on pin 11 (slp_tr) to actually start the transmission. this waiting state is signaled two symbol periods after the recep tion of the last symbol of a data or mac command frame by register bits trac_status ( register 0x 02, xah_ctrl_0), which are set to success_wait_for_ack in that case. in networks using slotted operation the start of the acknowledgment frame, and thus the exact timing , must be provided by the microcontroller. a timing example of an rx_aack transaction with register bit slotted_operation ( register 0x 2c, xah_ctrl_0) set is shown in figure 7 - 13 . the acknowledgement frame is ready to be transmitted two symbol times after the reception of the last symbol of a data or mac command frame . the transmission of the acknowledgement frame is initiated by the microcontroller with the rising edge of pin 11 (slp_tr) and starts t tr10 = 16 s later. the interrupt latency t irq is specified in section 12. 4 . figure 7 - 13 . example timing of an rx_aack transaction for slotted operation . r x / t x f r a m e o n a i r r x _ a a c k _ o n t r x _ s t a t e f r a m e t y p e r x _ a a c k _ o n r x / t x r x t x t r x _ e n d i r q r x t y p . p r o c e s s i n g d e l a y t i r q 5 1 2 0 7 0 4 t i m e [ s ] 6 4 1 0 2 6 d a t a f r a m e ( l e n g t h = 1 0 , a c k = 1 ) a c k f r a m e s f d 3 2 s ( 2 s y m b o l s ) s l p _ t r t t r 1 0 t x r x s l p _ t r a c k t r a n s m i s s i o n i n i t a t e d b y m i c r o c o n t r o l l e r b u s y _ r x _ a a c k r x w a i t i n g p e r i o d s i g n a l l e d b y r e g i s t e r b i t s t r a c _ s t a t u s
59 8351b C C AT86RF233 7.2.3.6 rx_aack mode timing a timing example of an rx_aack transaction is shown in figure 7 - 14 . in this example a data frame of length 10 with an ack request is received. the atmel AT86RF233 changes to state busy_rx_aack after sfd detection. the completion of the frame reception is indicated by an irq_3 ( trx_end ) interrupt. the i nterrupts irq_2 ( rx_start ) and irq_5 ( ami ) are disabled in this example. the ack frame is automatically transmitted after at urnaroundtime (12 symbols), assuming default acknowledgment frame start timing. the interrupt latency t irq is specified in section 12.4 . figure 7 - 14 . example timing of an rx_aack transaction . note: 1. if register bit aack_ack_time (register 0x17, xah_ctrl_1) is set, an acknow ledgment frame is sent already two symbol times after the reception of the last symbol of a data or mac command frame. r x / t x f r a m e o n a i r rx _ aack _ on busy _ rx _ aack trx _ state frame type rx _ aack _ on rx / tx rx tx trx _ end irq rx typ . processing delay t irq 512 0 704 time [ s ] 64 1088 data frame ( length = 10 , ack = 1 ) ack frame sfd 192 s ( 12 symbols )
60 8351b C C AT86RF233 7.2.4 tx_aret_on C transmit with automatic frame retransmission and csma - ca retry figure 7 - 15 . flow diagram of tx_aret . t r x _ s t a t e = t x _ a r e t _ o n c s m a _ r c t r = 0 t r x _ s t a t e = t x _ a r e t _ o n n y f a i l u r e s u c c e s s n y f r a m e _ r c t r = 0 t r a n s m i t f r a m e f r a m e _ r c t r = f r a m e _ r c t r + 1 y n n y t r a c _ s t a t u s = n o _ a c k t r a c _ s t a t u s = s u c c e s s t r a c _ s t a t u s = c h a n n e l _ a c c e s s _ f a i l u r e i s s u e i r q _ 3 ( t r x _ e n d ) i n t e r r u p t c c a r e s u l t a c k r e q u e s t e d a c k v a l i d t r a c _ s t a t u s = s u c c e s s _ d a t a _ p e n d i n g y n r e c e i v e a c k u n t i l t i m e o u t y n t r x _ s t a t e = b u s y _ t x _ a r e t t r a c _ s t a t u s = i n v a l i d m a x _ c s m a _ r e t r i e s < 7 y n c s m a _ r c t r > m a x _ c s m a _ r e t r i e s y n o t e 1 : i f m a x _ c s m a _ r e t r i e s = 7 n o r e t r y i s p e r f o r m e d ( s e e n o t e 1 ) r a n d o m b a c k - o f f c s m a _ r c t r = c s m a _ r c t r + 1 c c a s t a r t t x f r a m e _ r c t r > m a x _ f r a m e _ r e t r i e s d a t a p e n d i n g n
61 8351b C C AT86RF233 overview the implemented tx_aret algorithm is shown in figure 7 - 15 . in tx_aret mode , the atmel AT86RF233 first executes the csma - ca algorithm , as defined by ieee 802.15.4 C 2006 , section 7.5.1.4, initiated by a transmit start event. if the channel is idle a frame is transmitted from the frame buffer . if the acknowledgement frame is requested the radio transceiver additionally checks for an ack reply. t he completion of the tx_aret transmit transacti on is indicated by an irq_3 ( trx_end ) interrupt . description configuration and address bits are to be set in trx_off or pll_on state prior to switching to tx_a ret mode . it is further recommended to transfer the psdu data to the frame buffer in advance. the transaction is started by either using pin 11 ( slp_tr ), refer to section 6.6 , or writing a tx_start command to register bits trx_cmd ( register 0x 02 , trx_state). if the csma - ca detect s a busy channel, it is retried as specified by the register bits max_csma_retries ( re gister 0x 2c, xah_ctrl_0). in case that csma - ca does not detect a clear channel after max_csma_retries, it aborts the tx_aret transaction , issues interrupt irq_3 ( trx_end ) , and set the value of the register bits trac_status to channel_access_failure. during transmission of a frame the radio transceiver parses bit 5 ( ack request) of the mac header (mhr) frame control field of the psdu data (psdu octet #1) to be transmitted to check if an ack reply is expected. if an ack is expected , the radio transceiver automatically switches into receive mode to wait for a valid ack reply. after receiving an ack frame t he frame pending subfield of th at frame is parsed an d the status register bits trac_status are updated accordingly, refer to table 7 - 12 . this receive procedure does not overwrite the frame buffer content . transmit data in the frame buffer is not changed during the entire tx_aret transaction. received frames other than the expected ack frame are discarded. if no valid ack is received or a fter timeout of 54 symbol periods (864 s ) , the radio transceiver retries the entire transaction, ( including csma - ca ) until the maximum number of retransmissions (as set by the reg ister bits max_frame_retries ( register 0x 2c, xah_ctrl_0) ) is exceeded . the current csma - ca and frame r etransmission co unter values of an ongoing tx_aret transaction can be retrieved by the register bits aret_frame_retries and aret_csma_retries (register 0x19, xah_ctrl_2). additionally to the rx frame time stamping via pin 10 (dig2) , a tx frame time stamping within tx_aret mode can be activated, if the register bits irq_2_ext_en (register 0x04, trx_ctrl_1) and aret_tx_ts_en (register 0x17, xah_ctrl_1) are set to one , see section 11.6 . after that, the microcontroller may read the value of the register bits trac_status ( register 0x 02, trx_state) to verify whether the transaction was successful or not . the register bits are set according to the following cases , additional exit codes are described in section 7.2.6 :
62 8351b C C AT86RF233 table 7 - 12 . interpretation of trac_status r egister bi ts . value name description 0 success the transaction was responded to by a valid ack, or, if no ack is requested, after a successful frame transmission . 1 success_data_pending equivalent to success, indicates pending frame data according to the mhr frame control field of the received ack response . 3 channel_access_failure channel is still busy after attempting max_csma_retries of csma - ca . 5 no_ack no acknowledgement frames were received during all retry attempts . 7 invalid transaction not yet finished . if no ack is expected (according to the content of the received frame in the frame buffer) , the radio transceiver issues irq_3 ( trx_end ) directly after the frame transmission has been completed. the value of register bits trac_status ( register 0x 02, trx_state) is set to success. a value of max_csma_retries = 7 initiates an immediate tx_aret transaction without performing csma - ca. this can be used for example to transmit indirect data to a device. further the value max_frame_retries is ignored and the tx_aret transaction is performed only once. a timing example of a tx_aret transaction is shown in figure 7 - 16 . figure 7 - 16 . example timing of a tx_aret transaction . notes: 1. t csma - ca defines the random csma - ca backoff time. 2. timing figure t tr10 and t tr11 refer to table 7 - 1 . here an example data frame of length 10 with an ack request is transmitted. after that the atmel AT86RF233 switches to receive mode and expects an acknowledgement response . during the whole transaction including frame transmit, wait for ack and ack receive the radio transceiver status register bits trx_status ( register 0x 01, trx_status) signals busy_t x_aret. a successful reception of the acknowledgment frame is indicated by irq_3 ( trx_end ) . the status register bits trx_status ( register 0x 01, r x / t x f r a m e o n a i r tx _ aret _ on busy _ tx _ aret trx _ state frametype tx _ aret _ on rx / tx rx trx _ end irq typ . processing delay t tr 10 672 0 x time [ s ] 128 x + 352 slp _ tr tx t irq data frame ( length = 10 , ack = 1 ) ack frame t csma - ca tx csma - ca rx t tr 11
63 8351b C C AT86RF233 trx_stat us) ch anges back to tx_aret_on. t he register bits trac_status (register 0x02, trx_state) change to either trac_status = success , or trac_status = success_data_pending if the frame pending subfield of the received ack frame was set to one . 7.2.5 interrupt handling the atmel AT86RF233 interrupt handling in the extended operating mode is similar to the basic operating mode , refer to section 7.1.3 . the microcontroller enables interrupts by setting the appropriate bit in register 0x 0e (irq_mask). for rx_aack and tx_aret modes the following interrupts inform about the status of a frame reception and transmission : table 7 - 13 . interrupt handling in extended operating mode . mode interrupt description rx_aack irq_2 ( rx_start ) indi cates a phr reception irq_5 ( ami ) issued at address match irq_3 ( trx_end ) signals completion of rx_aack transaction if successful - a received frame must pass the address filter - the fcs is valid tx_aret irq_3 ( trx_end ) signals completion of tx_aret transaction rx_aack / tx_aret irq_0 ( pll_lock ) entering rx_aack _on or tx_aret _on state from trx_off state, the pll_lock interrupt signals that the transaction can be started rx_aack for support of the rx_aack functionality , it is recommended to enable irq_3 ( trx_end ) . this interrupt is issued only if frames passes the frame filtering, refer to section 7.2.3.4 , and has a valid fcs. this functionality differs in basic operating mode, refer to section 7.1.3 . the usage o f other interrupts is optional. on reception of a valid p hr an irq_2 ( rx_start ) is issued. irq_5 ( ami ) indicates address match, refer to filter rules in section 7.2.3.4 , and the completion of a frame reception with a valid fcs is indicated by interrupt irq_3 ( trx_end ) . thus, it can happen that an irq_2 ( rx_start ) and/or irq_5 ( ami ) are issued, but the irq_3 ( trx_end ) interrupt is never triggered when a frame does not pass the fcs computation check. tx_aret the irq_3 ( trx_end ) interrupt is always generated after completing a n tx_aret transaction. after that, the return code can be read from register bits trac_status (register 0x02, trx_state). several interrupts are automatically suppressed by the radio transceiver during tx_aret transaction. in contrast to section 8.5 , the cca algorithm (part of csma - ca) does not generate interrupt irq_ 4 ( cca_ed_done ) . furthermore, the interrupts irq_2 ( rx_start ) and/or irq_5 ( ami ) are not generated during the tx_aret acknowledgment receive p rocess. all other interrupts as described in section 6.7 , are also available in extended operating mode.
64 8351b C C AT86RF233 7.2.6 register summary the following atmel AT86RF233 registers are to be configured to control the extended operating mode: table 7 - 14 . register summary . reg. - addr. register name description 0x01 trx_status radio transceiver status, cca result 0x02 trx_state radio transceiver state control, tx_aret status 0x04 trx_ctrl_1 tx_auto_crc_on 0x08 phy_cc_cca cca mode control , see section 8.5.6 0x09 cca_thres cca ed threshold settings , see section 8.5.6 0x17 xah_ctrl_1 tx_aret and rx_aack control 0x1 9 xah_ctrl_ 2 tx_aret control 0x20 C 0x2b frame filter configuration - short address, pan id, and ieee address 0x2c xah_ctrl_0 tx_aret control, r etries value control 0x2d csma_seed_0 csma - ca seed value 0x2e csma_seed_1 csma - ca seed value, rx_aack control 0x2f csma_be csma - ca backoff exponent control 7.2.7 register description C control r egisters register 0x01 (trx_status): the read - only register trx_status signals the present state of the radio transceiver as well as the status of a cca operation. figure 7 - 17 . register trx_status. bit 7 6 5 4 0x01 cca_done cca_status reserved trx_status trx_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x01 trx_status trx_status read/write r r r r reset value 0 0 0 0 ? bit 4:0 - trx_status the register bits trx_status signal the current radio transceiver status. table 7 - 15 . trx_status. register bits value description trx_status 0x00 p_on 0x01 busy_rx 0x02 busy_tx 0x06 rx_on 0x08 trx_off (clk mode)
65 8351b C C AT86RF233 register bits value description 0x09 pll_on (tx_on) 0x0f (1) sleep 0x10 prep_deep_sleep 0x11 (2) busy_rx_aack 0x12 (2) busy_tx_aret 0x16 (2) rx_aack_on 0x19 (2) tx_aret_on 0x1f (3) state_transition_in_progress all other values are reserved notes: 1. in sleep or deep_sleep state register not accessible. 2. extended operating mode only. 3. do not try to initiate a further state change while the radio transceiver is in state_transition_in_progress state. a read access to trx_status register signals the current radio transceiver state. a state change is initiated by writing a state transit ion command to register bits trx_cmd (register 0x02, trx_state). alternatively , some state transition s can be initiated by the rising edge of pin 11 (slp_tr) in the appropriate state. register 0x02 (trx_state): the radio transceiver states are controlled via register trx_state using register bits trx_cmd. the read - only register bits trac_status indicate the status or result of an extended operating mode transaction. figure 7 - 18 . register trx_state. bit 7 6 5 4 0x02 trac_status trx_cmd trx_state read/write r r r r/w reset value 0 0 0 0 bit 3 2 1 0 0x02 trx_cmd trx_state read/write r/w r/w r/w r/w reset value 0 0 0 0
66 8351b C C AT86RF233 ? bit 7:5 C trac_status table 7 - 16 . trac_status. register bits value description rx_aack tx_aret trac_status 0 (1) success x x 1 success_data_pending x 2 success_wait_for_ack x 3 channel_access_failure x 5 no_ack x 7 (1) invalid x x all other values are reserved note : 1. even though the reset value for register bits trac_status is zero, the rx_aack and tx_aret procedures set the register bits to trac_status = 7 (invalid) when they are started. the status of the rx_aack and tx_aret procedure is indicated by register bits trac_status. values are meaningfull after an interrupt until the next frame transmit. details of the algorithm and a description of the status information are given in section 7.2.3 and section 7.2.4 . rx_aack success_wait_for_ack: indicates an ack frame is about to be sent in rx_aack slotted acknowledgement. slotted acknowledgement operation must be enabled with register bit slotted_operation (register 0x2c, xah_xtrl_0). the microcontroller must pulse pin 11 (s lp_tr) at the next backoff slot boundary in order to initiate a transmission of the ack frame. for details refer to ieee 802.15.4 - 2006, section 7.5.6.4.2. tx_aret success_data_pending: indicates a successful reception of an ack frame with frame pending bit set to one . ? bit 4:0 - trx_cmd a write access to register bits trx_cmd initiate a radio transceiver state transition to the new state. table 7 - 17 . trx_cmd. register bits value description trx_cmd 0x00 (1) nop 0x02 (2) tx_start 0x03 force_trx_off 0x04 (3) force_pll_on 0x06 rx_on 0x08 trx_off (clk mode)
67 8351b C C AT86RF233 register bits value description 0x09 pll_on (tx_on) 0x10 prep_deep_sleep 0x16 (4) rx_aack_on 0x19 (4) tx_aret_on all other values are reserved notes: 1. trx_cmd = D0 after power on reset (por). 2. the frame transmission starts one symbol after tx_start command. 3. force_pll_on is not valid for states p_on, sleep, deep_sleep, and reset, as well as state_transition_in_progress towards these states. 4. extended operating mode only. a successful state transition shall be confirmed by reading register bits trx_status (register 0x01, trx_status). the r egister bits trx_cmd are used for basic and extended operating mode s , refer to section 7.1 . register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver. figure 7 - 19 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 5 - tx_auto_crc_on the register bit tx_auto_crc_on controls the automatic fcs generation for transmit operations. table 7 - 18 . tx_auto_crc_on. register bits value description tx_auto_crc_on 0 automatic fcs generation is disabled 1 automatic fcs generation is enabled note: 1. the tx_auto_crc_on function can be used within basic and extended operating modes. for further details refer to section 8.2 .
68 8351b C C AT86RF233 register 0x17 (xah_ctrl_1): the xah_ctrl_1 register is a multi - purpose controls register for extended op erating mode. figure 7 - 20 . register xah_ctrl_1. bit 7 6 5 4 0x17 aret_tx_ts_en reserved aack_fltr_res_ ft aack_upld_res_ ft xah_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x17 reserved aack_ack_time aack_prom_ mode aack_spc_en xah_ctrl_1 read/write r r/w r/w r/w reset value 0 0 0 0 ? bit 7 - aret_tx_ts_en if register bit aret_tx_ts_en = 1, then any frame transmission within tx_aret mode is signaled via pin 10 (dig2). table 7 - 19 . aret_tx_ts_en. register bits value description aret_tx_ts_en 0 tx_aret time stamping via pin 10 (dig2) is disabled 1 (1) tx_aret time stamping via pin 10 (dig2) is enabled note: 1. it is necessary to set register bit irq_2_ext_en (register 0x04, trx_ctrl_1). ? bit 5 - aack_fltr_res_ft filter reserved frame types like data frame type. the register bit aack_fltr_res_ft shall only be set if register bit aack_upld_res_ft = 1. table 7 - 20 . aack_fltr_res_ft. register bits value description aack_fltr_res_ft 0 (1) filtering reserved frame types is disabled 1 (2) filtering reserved frame types is enabled notes: 1. if aack_fltr_res_ft = 0 the received reserved frame is only checked for a valid fcs. 2. if aack_fltr_res_ft = 1 reserved frame types are filtered similar to data frames as specified in ieee 802.15.4 C 2006. reserved frame types are explained in i eee 802.15.4 section 7.2.1.1.1.
69 8351b C C AT86RF233 ? bit 4 - aack_upld_res_ft upload reserved frame types within rx_aack mode. table 7 - 21 . aack_upld_res_ft. register bits value description aack_upld_res_ft 0 upload of reserved frame types is disabled 1 (1) upload of reserved frame types is enabled note: 1. if aack_upld_res_ft = 1 received frames indicated as a reserved frame are further processed. for those frames, an irq_3 (trx_end) interrupt is generated if the fcs is valid. in conjunction with the configuration bit aack_fltr_res_ft, these frames are handled like ieee 802.15.4 compliant data frames during rx_aack transaction. an irq_5 ( ami ) inter rupt is issued, if the addresses in the received frame match the nodes addresses. that means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. if this is not wanted register bit aack_dis_ack ( register 0x 2e, csma_seed_1) has to be set. ? bit 2 - aack_ack_time the register bit aack_ack_time controls the acknowledgment frame response time within rx_aack mode. table 7 - 22 . aack_ack_time. register bits value description aack_ack_time 0 acknowledgment time is 12 symbol periods (aturnaroundtime) 1 acknowledgment time is two symbol periods according to ieee 802.15.4 - 2006 , section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aturnaroundtime) after the reception of the last symbol of a data or mac command frame . this is achieved with the reset value of the register bit aack_ack_time. alterna tively, i f aack_ack_time = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or mac command frame . this may be applied to proprietary networks or networks using the h igh d ata r ate mode s to increase battery lifetime and to improve the overall data throughput; refer to section 11.3 . ? bit 1 - aack_prom_mode the register bit aack_prom_mode enables the promiscuous mode, within the rx_aack mode. table 7 - 23 . aack_prom_mode. register bits value description aack_prom_mode 0 promiscuous mode is disabled 1 promiscuous mode is enabled r efer to ieee 802.15.4 - 2006 section 7.5.6.5.
70 8351b C C AT86RF233 if this register bit is set, every incoming frame with a valid p hr finishes with irq_3 ( trx_end ) interrupt even if the third level filter rules do not match or the fcs is not valid . however, register bit rx_crc_valid ( register 0x 06, phy_rssi ) is set accordingly . in contrast to ieee 802.15.4 - 2006 , if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit aack_dis_ack ( register 0x 2e, csma_seed_1) , or use basic operating mode instead. regis ter 0x19 (xah_ctrl_2): the read - only register xah_ctrl_2 retrieves the current counter values for extended operating mode. figure 7 - 21 . register xah_ctrl_2. bit 7 6 5 4 0x19 aret_frame_retries xah_ctrl_2 read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x19 aret_csma_retries reserved xah_ctrl_2 read/write r r r r reset value 0 0 0 0 ? bit 7:4 - aret_frame_retries retrieves current frame retry counter value. table 7 - 24 . aret_frame_retries. register bits value description aret_frame_retrie s 0x0 minimum possible frame retry counter value 0xf maximum possible frame retry counter value note: 1. a new cca_backoff cycle or new frame transmit cycle changed these value. ? bit 3:1 - aret_csma_retries retrieves current csma - ca retry counter value. table 7 - 25 . aret_csma_retries. register bits value descri ption aret_csma_retries 0 minimum possible csma - ca retry counter value 5 maximum possible csma - ca retry counter value note: 1. a new cca_backoff cycle or new frame transmit cycle changed these value.
71 8351b C C AT86RF233 register 0x2c (xah_ctrl_0): the xah_ctrl_0 register is a control register for extended operating mode. figure 7 - 22 . register xah_ctrl_0. bit 7 6 5 4 0x2c max_frame_retries xah_ctrl_0 read/write r/w r/w r/w r/w reset value 0 0 1 1 bit 3 2 1 0 0x2c max_csma_retries slotted_ operation xah_ctrl_0 read/write r/w r/w r/w r/w reset value 1 0 0 0 ? bit 7:4 - max_frame_retries number of retransmission attempts in tx_aret mode before the transaction gets cancelled. table 7 - 26 . max_frame_retries. register bits value description max_frame_retries 0x3 the setting of max_frame_retries in tx_aret mode specifies the number of attempts to retransmit a frame, when it was not acknowle dged by the recipient, before the transaction gets cancelled. valid values are [0x7, 0x6, , 0x0]. ? bit 3:1 - max_csma_retries number of retries in tx_aret mode to repeat the csma - ca procedure before the transaction gets cancelled. table 7 - 27 . max_csma_retries. register bits value description max_csma_retries 0 (1) no retries 1 (1) one retry 2 (1) two retries 3 (1) three retries 4 (1) four retries 5 (1) five retries 7 (3) immediate frame transmission without performing csma - ca notes: 1. max_csma_retries specifies the number of retries in tx_aret mode to repeat the csma - ca procedure before the transaction gets cancelled. according to ieee 802.15.4 the valid range of max_csma_retries is [5, 4, , 0]. 2. max_csma_retries = 6 is reserved. 3. a value of max_csma_retries = 7 initiates an immediate frame transmission without performing csma - ca. no retry is performed. this may especially be required for slotted acknowledgement operation.
72 8351b C C AT86RF233 ? bit 0 - slotted_operation for rx_aack mode, the register bit slotted_operation determines, if the transceiver will require a time base for slotted operation. table 7 - 28 . slotted_operation. register bits value description slotted_operation 0 the radio transceiver operates in unslotted mode. an acknowledgment frame is automatically sent if requested. 1 the transmission of an acknowledgement frame has to be controlled by the microcontroller. u sing rx_aack mode in networks operating in beacon or slotted mode, refer to ieee 802.15.4 - 2006, section 5.5.1 , register bi t slotted_operation indicates that acknowledgement frames are to be sent on backoff slot boundaries (slotted acknowledgement) , refer to section 7.2. 3.5 . if this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using the rising edge of pin 11 (slp_tr ) . this waiting state is signaled in regi ster bits trac_status ( register 0x 02, trx_state) with value success_wait_for_ack. register 0x2d (csma_seed_0): the register csma_seed_0 contains the lower 8 - bit of csma_seed. figure 7 - 23 . register csma_seed_0. bit 7 6 5 4 0x2d csma_seed_0 csma_seed_0 read/write r/w r/w r/w r/w reset value 1 1 1 0 bit 3 2 1 0 0x2d csma_seed_0 csma_seed_0 read/write r/w r/w r/w r/w reset value 1 0 1 0 ? bit 7:0 - csma_seed_0 lower 8 - bit of csma_seed, bits[7:0]. used as seed for random number generation in the csma - ca algorithm. table 7 - 29 . csma_seed_0. register bits value description csma_seed_0 0xea this register contains the lower 8 - bit of the csma_seed, bits[7:0]. the higher 3 - bit are part of register bits csma_seed_1 (register 0x2e, csma_seed_1). csma_seed is the seed for the random number generation that determines the length of the backoff period in the csma - ca algorithm.
73 8351b C C AT86RF233 note s : 1. it is rec ommended to initialize register bits csma_seed_0 and csma_seed_1 with random values. this can be done using register bits rnd_value (regi ster 0x06, phy_rssi), refer to section 11.2 . 2. the content of register bits csma_seed_0 and csma_seed_1 initializes the tx_aret random backoff generator after wakeup from deep_ sleep state. it is recommended to reinitialize both registers after every deep_ sleep state with a random value. register 0x2e (csma_seed_1): the csma_seed_1 register is a control register for rx_aack and contains a part of the csma_seed for the csma - ca a lgorithm. figure 7 - 24 . register csma_seed_1. bit 7 6 5 4 0x2e aack_fvn_mode aack_set_pd aack_dis_ack csma_seed_1 read/write r/w r/w r/w r/w reset value 0 1 0 0 bit 3 2 1 0 0x2e aack_i_am_ coord csma_seed_1 csma_seed_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 7:6 - aack_fvn_mode the register bits aack_fvn_mode control the ack behavior dependent on fcf frame version number within rx_aack mode. table 7 - 30 . aack_fvn_mode. register bits value description aack_fvn_mode 0 accept frames with version number 0 1 accept frames with version number 0 or 1 2 accept frames with version number 0 or 1 or 2 3 accept frames independent of frame version number note: 1. aack_fvn_mode value one indicates frames according to ieee 802.15.4 C 2006, a value of three indicates frames according to ieee 802.15.4 C 2003 standard. the frame control field of the mac header (mhr) contains a frame version subfield. the setting of register bits aack_fvn_mode specifies the frame filtering behavior of the atmel AT86RF233 . according to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. thus the register bit s aack_fvn_mode defines the maximum acceptable frame version. received frames with a higher frame version number than configured do not pass the frame filter and are not acknowledged. the frame version field of the acknowledg m e nt frame is set to zero according to ieee 802.15.4 - 2006, section 7.2.2.3.1 acknowl edgment frame mhr fields .
74 8351b C C AT86RF233 ? bit 5 - aack_set_pd the content of aack_set_pd bit is copied into the frame pending subfield of the acknowledgment frame if the ack is the response to a data request mac command frame. table 7 - 31 . aack_set_pd. register bits value description aack_set_pd 0 pending data bit set to zero 1 pending data bit set to one in addition, if register bits aack_fvn_mode ( register 0x 2e, csma_seed_1) are configured to accept frames with a frame version other than zero or one , the content of register bit aack_set_pd is also copied into the frame pending subfield of the acknowledgment frame for any mac command frame with a frame version of two or three that have the security enabled subfield set to one . this is done in the assumption that a future version of the ieee 802.15.4 - 2006 [ 2 ] standard might change the length or structure of the auxiliary security header . ? bit 4 - aack_dis_ack if this bit is set no acknowledgment frames are transmitted in rx_aack extended operating mode, e ven if requested. table 7 - 32 . aack_dis_ack. register bits value description aack_dis_ack 0 acknowledgment frames are transmitted 1 acknowledgment frames are not transmitted ? bit 3 - aack_i_am_coord this register bit has to be set if the node is a pan coordinator. it is used for frame filtering in rx_aack. table 7 - 33 . aack_i_am_coord. register bits value description aack_i_am_coord 0 pan coordinator addressing is disabled 1 pan coordinator addressing is enabled if aack_i_am_coord = 1 and i f only source addressing fields are included in a data or mac command frame , the frame shall be accepted only if the device is the pan coordinator and the source pan identifier matches macpanid , for details refer to ieee 802.15.4 - 2006, section 7.5.6.2 ( third - level filter rule six ) .
75 8351b C C AT86RF233 ? bit 2:0 - csma_seed_1 higher 3 - bit of csma_seed, bits[10:8]. seed for random number generation in the csma - ca algorithm. table 7 - 34 . csma_seed_1. register bits value description csma_seed_1 2 these register bits are the higher 3 - bit of the csma_seed, bits [10:8]. the lower part is in register 0x2d (csma_seed_0), see register csma_seed_0 for details. register 0x2f (csma_be): the register csma_be contains the backoff exponents for the csma - ca algorithm. figure 7 - 25 . register csma_be. bit 7 6 5 4 0x2f max_be csma_be read/write r/w r/w r/w r/w reset value 0 1 0 1 bit 3 2 1 0 0x2f min_be csma_be read/write r/w r/w r/w r/w reset value 0 0 1 1 note: 1. if min_be = 0 and max_be = 0 the cca backoff period is always set to zero. ? bit 7:4 - max_be maximum backoff exponent in the csma - ca algorithm. table 7 - 35 . max_be. register bits value description max_be 0x5 register bits max_be defines the maximum backoff exponent used in the csma - ca algorithm to generate a pseudo random number for cca backoff. valid values are [0x8, 0x7, , 0x0]. for details refer to ieee 802.15.4 - 2006, section 7.5.1.4. ? bit 3:0 - min_be minimum backoff exponent in the csma - ca algorithm. table 7 - 36 . min_be. register bits value de scription min_be 0x3 register bits min_be defines the minimum backoff exponent used in the csma - ca algorithm to generate a pseudo random number for cca backoff. valid values are [max_be, (max_be C 1), , 0x0]. for details refer to ieee 802.15.4 - 2006, section 7.5.1.4.
76 8351b C C AT86RF233 7.2.8 register description C address registers register 0x20 (short_addr_0): this register contains the lower 8 - bit of the mac short address for frame filter address recognition, bits[7:0]. figure 7 - 26 . register short_addr_0. bit 7 6 5 4 0x20 short_addr_0 short_addr_0 read/write r/w r/w r/w r/w reset value 1 1 1 1 bit 3 2 1 0 0x20 short_addr_0 short_addr_0 read/write r/w r/w r/w r/w reset value 1 1 1 1 register 0x21 (short_addr_1): this register contains the higher 8 - bit of the mac short address for frame filter address recognition, bits[15:8]. figure 7 - 27 . register short_addr_1. bit 7 6 5 4 0x21 short_addr_1 short_addr_1 read/write r/w r/w r/w r/w reset value 1 1 1 1 bit 3 2 1 0 0x21 short_addr_1 short_addr_1 read/write r/w r/w r/w r/w reset value 1 1 1 1 register 0x22 (pan_id_0): this register contains the lower 8 - bit of the mac pan id for frame filter address recognition, bits[7:0]. figure 7 - 28 . register pan_id_0. bit 7 6 5 4 0x22 pan_id_0 pan_id_0 read/write r/w r/w r/w r/w reset value 1 1 1 1 bit 3 2 1 0 0x22 pan_id_0 pan_id_0 read/write r/w r/w r/w r/w reset value 1 1 1 1
77 8351b C C AT86RF233 register 0x23 (pan_id_1): this register contains the higher 8 - bit of the mac pan id for frame filter address recognition, bits[15:8]. figure 7 - 29 . register pan_id_1. bit 7 6 5 4 0x23 pan_id_1 pan_id_1 read/write r/w r/w r/w r/w reset value 1 1 1 1 bit 3 2 1 0 0x23 pan_id_1 pan_id_1 read/write r/w r/w r/w r/w reset value 1 1 1 1 register 0x24 (ieee_addr_0): this register contains the lower 8 - bit of the mac ieee address for frame filter address recognition, bits[7:0]. figure 7 - 30 . register ieee_addr_0. bit 7 6 5 4 0x24 ieee_addr_0 ieee_addr_0 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x24 ieee_addr_0 ieee_addr_0 read/write r/w r/w r/w r/w reset value 0 0 0 0 register 0x25 (ieee_addr_1): this register contains 8 - bit of the mac ieee address for frame filter address recognition, bits[15:8]. figure 7 - 31 . register ieee_addr_1. bit 7 6 5 4 0x25 ieee_addr_1 ieee_addr_1 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x25 ieee_addr_1 ieee_addr_1 read/write r/w r/w r/w r/w reset value 0 0 0 0
78 8351b C C AT86RF233 register 0x26 (ieee_addr_2): this register contains 8 - bit of the mac ieee address for frame filter address recognition, bits[23:16]. figure 7 - 32 . register ieee_addr_2. bit 7 6 5 4 0x26 ieee_addr_2 ieee_addr_2 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x26 ieee_addr_2 ieee_addr_2 read/write r/w r/w r/w r/w reset value 0 0 0 0 register 0x27 (ieee_addr_3): this register contains 8 - bit of the mac ieee address for frame filter address recognition, bits[31:24]. figure 7 - 33 . register ieee_addr_3. bit 7 6 5 4 0x27 ieee_addr_3 ieee_addr_3 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x27 ieee_addr_3 ieee_addr_3 read/write r/w r/w r/w r/w reset value 0 0 0 0 register 0x28 (ieee_addr_4): this register contains 8 - bit of the mac ieee address for frame filter address recognition, bits[39:32]. figure 7 - 34 . register ieee_addr_4. bit 7 6 5 4 0x28 ieee_addr_4 ieee_addr_4 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x28 ieee_addr_4 ieee_addr_4 read/write r/w r/w r/w r/w reset value 0 0 0 0
79 8351b C C AT86RF233 register 0x29 (ieee_addr_5): this register contains 8 - bit of the mac ieee address for frame filter address recognition, bits[47:40]. figure 7 - 35 . register ieee_addr_5. bit 7 6 5 4 0x29 ieee_addr_5 ieee_addr_5 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x29 ieee_addr_5 ieee_addr_5 read/write r/w r/w r/w r/w reset value 0 0 0 0 register 0x2a (ieee_addr_6): this register contains 8 - bit of the mac ieee address for frame filter address recognition, bits[55:48]. figure 7 - 36 . register ieee_addr_6. bit 7 6 5 4 0x2a ieee_addr_6 ieee_addr_6 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x2a ieee_addr_6 ieee_addr_6 read/write r/w r/w r/w r/w reset value 0 0 0 0 register 0x2b (ieee_addr_7): this register contains the higher 8 - bit of the mac ieee frame filter address for address recognition, bits[63:56]. figure 7 - 37 . register ieee_addr_7. bit 7 6 5 4 0x2b ieee_addr_7 ieee_addr_7 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x2b ieee_addr_7 ieee_addr_7 read/write r/w r/w r/w r/w reset value 0 0 0 0
80 8351b C C AT86RF233 8 functional description 8.1 introduction C ieee 802.15.4 - 2006 frame format figure 8 - 1 provides an overview of the physical layer (phy) frame structure as defined by the ieee 802.15.4 - 2006 standard . figure 8 - 2 shows the frame structure of the medium access control ( mac ) layer . figure 8 - 1 . ieee 802.15.4 frame format - phy - layer frame structure (ppdu) . 8.1.1 phy protocol data unit (ppdu) 8.1.1.1 synchronization header (shr) the shr consists of a four - octet preamble field (all zero), followed by a single byte start - of - frame delimiter ( sfd ) which has the predefined value 0xa7. during transmi ssion , the shr is automatically generated by the atmel AT86RF233 , thus the frame buffer shall contain phr and psdu only , see section 6.3.2 . the transmission of the shr requires 160 s (10 symbols). as the spi data rate is normally higher than the over - air data rate, this allows the microcontroller to initiate a transmission without having transferred the full frame data already. instead it is possible to subsequently write the frame content. during f rame reception, the shr is used for synchronization purposes. the matching sfd determine s the beginning of the phr and the following psdu payload data . 8.1.1.2 phy header (phr) the phy header is a single octet following the shr. the least significant seven bits de note the frame length of the following psdu, while the most significant bit of that octet is reserved, and shall be set to zero for ieee 802.15.4 compliant frames . on reception, the phr is returned as the first octet during frame buffer read access. while the ieee 802.15.4 - 2006 standard declares bit seven of the phr octet as being reserved, the AT86RF233 preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. nevertheless, this bit is not considered to be part of the frame length, so only frames between one and 127 octets are possibl e. for ieee 802.15.4 compliant operation bit [7] has to be masked by software . in transmit mode, the phr needs to be supplied as the first octet during frame buffer write access, see section 6.3.2 . in receive mode, the phr ( that is frame length greater than zero ) is returned as the first octet during frame buffer read access (see section 6.3.2 ) and is signaled by an interrupt irq_2 ( rx_start ) . m a x i m u m 1 2 7 o c t e t s p h y s e r v i c e d a t a u n i t ( p s d u ) 1 o c t e t ( p h r ) 5 o c t e t s s y n c h r o n i z a t i o n h e a d e r ( s h r ) p h y p r o t o c o l d a t a u n i t ( p p d u ) p r e a m b l e s e q u e n c e s f d f r a m e l e n g t h p h y p a y l o a d m a c p r o t o c o l d a t a u n i t ( m p d u )
81 8351b C C AT86RF233 8.1.1.3 phy payload (phy service data unit, psdu) the psdu has a variable length between zero and amaxphypacketsize (127, maximum psdu size in octets). the length of the psdu is signaled by the frame length field (phr), refer to table 8 - 1 . the psdu contains the mac protocol data unit (mpdu), where the last two octets are used for the f rame ch eck sequence (fcs), see section 8.2 . received frames with a frame length field set to zero (invalid phr) are not signaled to the microcontroller. table 8 - 1 summarizes the type of payload versus the frame length value. table 8 - 1 . frame length field C ph r . frame length value payload 0 - 4 reserved 5 mpdu (acknowledgement) 6 C 8 reserved 9 - amaxphypacketsize mpdu 8.1.1.4 timing summary table 8 - 2 shows timing information for the above mentioned frame structure depending on the selected data rate. table 8 - 2 . ppdu timing . phy mode psdu bit rate [kb /s] header bit rate [kb /s] duration shr [s] phr [s] max. psdu [ms] o - qpsk (1) 250 250 160 32 4.064 o - qpsk (2) 500 250 160 32 2.032 1000 250 160 32 1.016 2 000 250 160 32 0.508 notes: 1. compliant to ieee 802.15.4 - 2006 [ 2 ] . 2. high data rate modes, see section 11.3 .
82 8351b C C AT86RF233 8.1.2 mac protocol data unit (mpdu) figure 8 - 2 shows the frame structure of the mac layer. figure 8 - 2 . ieee 802.15.4 - 2006 frame format - mac - layer frame structure (mpdu) . 8.1.2.1 mac header (mhr) fields the mac header consists of the frame control field (fcf), a sequence number, and the addressing fields (which are of variable length, and can even be empty in certain situations). 8.1.2.2 frame control field (fcf) the fcf consists of 16 bits, and occupies the firs t two octets of the mpdu or psdu, respectively . figure 8 - 3 . ieee 802.15.4 - 2006 frame control field (fcf) . bit [2:0] : describes the D f rame t ype D . table 8 - 3 summarizes frame types defined by ieee 802.15.4 - 2006 [ 2 ] , section 7. 2.1.1. 1 . table 8 - 3 . frame control field C frame type subfield . frame control field bit assignments description frame type value b 2 b 1 b 0 value 000 0 beacon 001 1 data 010 2 acknowledge 011 3 mac command 100 C 111 4 C 7 reserved f r a m e c o n t r o l f i e l d 2 o c t e t s f r a m e p e n d i n g r e s e r v e d f r a m e v e r s i o n a c k r e q u e s t p a n i d c o m p . d e s t i n a t i o n a d d r e s s i n g m o d e s o u r c e a d d r e s s i n g m o d e s e c . e n a b l e d ( m f r ) m a c s e r v i c e d a t a u n i t ( m s d u ) m a c p r o t o c o l d a t a u n i t ( m p d u ) m a c p a y l o a d f c s f r a m e t y p e 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 m a c h e a d e r ( m h r ) f c f a d d r e s s i n g f i e l d s s e q u e n c e n u m b e r 2 o c t e t s c r c - 1 6 0 / 5 / 6 / 1 0 / 1 4 o c t e t s a u x i l i a r y s e c u r i t y h e a d e r 0 / 4 / 6 / 8 / 1 0 / 1 2 / 1 4 / 1 6 / 1 8 / 2 0 o c t e t s d e s t i n a t i o n p a n i d d e s t i n a t i o n a d d r e s s s o u r c e p a n i d s o u r c e a d d r e s s f r a m e c o n t r o l f i e l d 2 o c t e t s f r a m e p e n d i n g r e s e r v e d f r a m e v e r s i o n a c k r e q u e s t p a n i d c o m p . d e s t i n a t i o n a d d r e s s i n g m o d e s o u r c e a d d r e s s i n g m o d e s e c . e n a b l e d f r a m e t y p e 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5
83 8351b C C AT86RF233 th is subfield is used for frame filtering by the third level filter rules. by default, o nly frame types 0 C 3 pass the third level filter rules , refer to section 7.2.3.4 . automatic frame filtering by the atmel AT86RF233 is enabled when using the rx_aack mode, refer to section 7.2.3 . however, a reserved frame (frame type value > 3) can be received if register bit aack_upld_res_ft ( register 0x 17, xah_ctrl_1) is set , for details refer to section 7.2.3.3 . f rame filtering is also provided in basic operating mode, refer to section 7.1 . bit 3 : indicates whether security processing applies to this frame. this field is evaluated by the frame filter. bit 4 : is th e Dframe p ending subfield. this field can be set in an acknowledgment frame (ack) in response to a data request mac command frame. this bit indicates that the node, which transmitted the ack, might have more data to send to the node receiving the ack. note : 1. for acknowledgment frames automatically generated by the AT86RF233 , this bit is set according to the content of register bit aack_set_pd in register 0x2e (csma_seed_1) if the received frame was a data request mac command frame. bit 5 : forms the D a cknowledgment r equest subfield. if this bit is set within a data or mac command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by ieee 802.15.4 ( that is within 192 s for non beacon - enabled networks). the radio transceiver parses this bit during rx_aack mode and transmits an acknowledgment frame if necessary. in tx_aret mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. if this is the case, the receiver waits for the acknowledgment frame, otherwise the tx_aret transaction is finished. bit 6 : the Dpan id compression subfield indicates that in a frame , where both, the destination and source addresses are present, the pan - id of the source address field is omitted. i n rx_aack mode , t his bit is evaluated by the address filter logic of the atmel AT86RF233 . this subfield was previously named Dintra - pan. bit [11:10] : the Ddestination a ddress ing m ode subfield describes the forma t of the destination address of the frame. the values of the address modes are summarized in table 8 - 4 , according to ieee 802.15.4. table 8 - 4 . frame control field C d estination and source addressing mode . frame control field bit assignments descr iption addressing mode b 11 b 10 b 15 b 14 value 00 0 pan identifier and address fields are not present 01 1 reserved 10 2 address field contains a 16 - bit short address 11 3 address field contains a 64 - bit extended address
84 8351b C C AT86RF233 if the destination address mode is either two or three ( that is if the destination address is present), it always consists of a 16 - bit pan - id first, followed by either the 16 - bit or 64 - bit address as described by the mode. bit [13:12] : the Dframe v ersion subfield specifies the version number corresponding to the frame. these register bits are reserved in ieee 802.15.4 - 2003. this subfield shall be set to zero to indicate a frame compatible with ieee 802.15.4 - 2003 and one to indicate an ieee 802.15.4 - 2006 fr ame. all other subfield values sh all be reserved for future use. rx_aack register bit s aack_fvn_mode ( register 0x 2e, csma_seed_1) controls the behavior of frame acknowledgements. this register determines if, depending on the frame version number, a frame is acknowledged or not. this is necessary for backward compatibility to ieee 802.15.4 - 2003 and for future use. even if frame version numbers two and three are reserved, it can be handled by the radio transceiver, for d etails refer to section 7.2.7 . see ieee 802.15.4 - 2006, section 7.2.3 for details on frame compatibility. table 8 - 5 . frame control field C frame version subfield . frame control field bit assignments description frame v ersion b 13 b 12 value 00 0 frames are compatible with ieee 802.15.4 - 2003 01 1 frames are compatible with ieee 802.15.4 - 2006 10 2 reserved 11 3 reserved bit [15:14] : the Dsource addressing mode subfield, with similar meaning as Ddestination addressing mode , see table 8 - 4 . the subfields of the fcf (bits 0 C 2, 3, 6, 10 C 15 ) affect the address filter logic of the AT86RF233 while operating in rx_aack operation , see section 7 .2.3 .
85 8351b C C AT86RF233 8.1.2.3 frame compatibility between ieee 802.15.4 - 2003 and ieee 802.15.4 - 2006 all unsecured frames according to ieee 802.15.4 - 2006 are compa tible with unsecured frames com pliant with ieee 802.15.4 - 2003 with two exceptions: a coordinator realignment command frame with the D channel page field present (see ieee 802.15.4 - 2006 , section 7.3.8) and any frame with a mac payload field larger than amaxmacsafepayloadsize octets . compatibility for secured frames is shown in table 8 - 6 , which identifies the security operating modes for ieee 802.15.4 - 2003 and ieee 802.15.4 - 2006 . table 8 - 6 . frame control field C security and frame version . frame control field bit assignments description security e nabled b 3 frame v ersio n b 13 b 12 0 00 no security. frames are compatible between ieee 802.15.4 - 2003 and ieee 802.15.4 - 2006. 0 01 no security. frames are not compatible between ieee 802.15.4 - 2003 and ieee 802.15.4 - 2006. 1 00 secured frame formatted according to ieee 802.15.4 - 2003. this frame type is not supported in ieee 802.15.4 - 2006. 1 01 secured frame formatted according to ieee 802.15.4 - 2006 . 8.1.2.4 sequence number the one - octet sequence number following the fcf identifies a particular frame, so that duplicated frame transmissions can be detected. while operating in rx_aack mode , the content of this field is copied from the frame to be acknowledged into the acknowled gment frame. 8.1.2.5 addressing fields the addressing field s of the mpdu are used by the atmel AT86RF233 for address matching indication. the destination address (if present) is always first, followed by the source address (if present). each address field consists of the pan - id and a device address. if both addresses are present, and the Dpan id compression subfield in the fcf is set to one , the source pan - id is omitted. note that in addition to these general rules, ieee 802.15.4 further restricts the valid address combinations for the individual possible mac frame types. for example, the situation where both addresses are omitted (source ad dressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. the address filter in the AT86RF233 has been des igned to apply to ieee 802.15.4 compliant frames. it can be configu red to handle other frame formats and exceptions. 8.1.2.6 auxiliary security header f ield the auxiliary security header specifies information required for security processing and has a variable length . this field determines how the frame is actually protected (security level) and which keying material from the mac security pib is used (see ieee 802.15.4 - 2006, section 7.6.1). this field shall be present only if the security enabled subfield b3, see section 8.1.2.3 , is set to one. for details of its structure , see ieee 802.15.4 - 2006, section 7.6.2 auxiliary security header .
86 8351b C C AT86RF233 8.1.2.7 mac service data unit (msdu ) this is the actual mac payload. it is usually structured according to the individual frame type . a description can be found in ieee 802.15.4 - 2006, section 5.5.3.2 . 8.1.2.8 mac footer (mfr) fields the mac footer consists of a two - octet frame checksum (fcs), for details refer to section 8.2 . 8.2 frame check sequence (fcs) t he frame check sequence ( fcs ) is characterized by : ? indicate bit errors , based on a cyclic redundancy check (crc) of length 16 bit ? uses international telecommunication union (itu) crc polynomial ? automatically evaluated during reception ? can be automatically generated during transmission 8.2.1 overview the fcs is intended for use at the mac layer to detect corrupted frames at a first level of filtering . it is computed by applying an itu crc polynomial to all transferred bytes following the length field (mhr and msdu fields). the frame check sequence has a length of 16 bit and is locat ed in the last two bytes of a frame (mac footer, see figure 8 - 2 ) . the atmel AT86RF233 applies an fcs check on each received frame. the fcs check result is stored in register bit rx_crc_valid ( register 0x06, phy_rssi). on transmission the radio transceiver generates and appends the fcs bytes during the frame transmission . this behavior can be disabled by setting register bit tx_auto_crc_on = 0 ( register 0x 04, trx_ctrl_1). 8.2.2 crc c alculation the crc polynomial used in ieee 802.15.4 networks is defined by . the fcs shall be calculated for transmission using the following algorithm: let be the polynomial representing the sequence of bits for which the checksum is to be computed. multiply m(x) by , giving the polynom ial . divide modulo two by the generator polynomial , , to obtain the remainder polynomial, . the fcs field is given by the coefficients of the remainder polynomial , r(x) . example: considering a five octet ack frame. the mhr field consists of 0100 0000 0000 0000 0101 0110. 1 ) ( 5 12 16 16 ? ? ? ? x x x x g 1 2 2 1 1 0 ) ( ? ? ? ? ? ? ? ? ? k k k k b x b x b x b x m ? 16 x 16 ) ( ) ( x x m x n ? ? ) ( x n ) ( 16 x g 15 14 14 1 15 0 ... ) ( r x r x r x r x r ? ? ? ? ?
87 8351b C C AT86RF233 the leftmost bit (b 0 ) is transmitted first in time. the fcs is in this case 0010 0111 1001 1110. the leftmost bit ( r 0 ) is transmitted first in time. 8.2.3 automatic fcs g eneration the automatic fcs generation is activated with register bit tx_auto_crc_on = 1 . this allows the atmel AT86RF233 to compute the fcs autonomously. for a frame with a frame length specified as n (3 n 127), the fcs is calculated on the first n - 2 octets in the frame buffer, and the resulting fcs field is transmitted in place of the last two octets from the frame buffer. if the radio transceiver s automatic fcs generation is enabled, the frame buffer write access can be stopped right after mac payload. there is no need to write fcs dummy bytes. in rx_aack mode , when a received frame needs to be acknowledged, the fcs of the ack frame is always automatically generated by the AT86RF233 , independent of the tx_auto_crc_on setting. example: a frame transmission of length five with tx_auto_crc_on set, is started with a frame buffer write access of five bytes (the last two bytes can be omitted). the first three bytes are used for fcs generation; the last two bytes are replaced by the internally calculated fcs. 8.2.4 automatic fcs c heck a n automatic fcs check is applied on each received frame with a frame length n 2 . register bit rx_crc_valid ( register 0x 06, phy _rssi) is set if the fcs of a received frame is valid . the register bit is updated when issuing interrupt irq_3 ( trx_end ) and remain s valid until the next trx_end interrupt caused by a new frame reception . in rx_aack mode , if fcs of the received frame is not valid, the radio transceiver rejects the frame and the trx_end interrupt is not issued . in tx_aret mode , the fcs and the sequence number of an ack is automatically checked. if one of these is not correct, the ack is not accepted. 8.2.5 register description register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver.
88 8351b C C AT86RF233 figure 8 - 4 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 5 - tx_auto_crc_on the register bit tx_auto_crc_on controls the automatic fcs generation for transmit operations. table 8 - 7 . tx_auto_crc_on. register bits value description tx_auto_crc_on 0 automatic fcs generation is disabled 1 automatic fcs generation is enabled note: 1. the tx_auto_crc_on function can be used within basic and extended operating modes. register 0x06 (phy_rssi): the phy_rssi register is a multi - purpose register that indicates fcs validity, to provide random numbers, and a rssi value. figure 8 - 5 . register phy_rssi. bit 7 6 5 4 0x06 rx_crc_valid rnd_value rssi phy_rssi read/write r r r r reset value 0 1 1 0 bit 3 2 1 0 0x06 rssi phy_rssi read/write r r r r reset value 0 0 0 0 ? bit 7 - rx_crc_valid the register bit rx_crc_valid signals the fcs check status for a received frame. table 8 - 8 . rx_crc_valid. register bits value description rx_crc_valid 0 fcs is not valid 1 fcs is valid reading this register bit indicates whether the last received frame has a valid fcs or not. the register bit is updated when issuing interrupt irq_3 ( trx_end ) and remains valid until the next trx_end interrupt is issued, caused by a new frame reception.
89 8351b C C AT86RF233 8.3 received signal strength indicator (rssi) the received signal strength indicator is characterized by : ? minimum rssi level is - 91 db m ( rssi base_val ) ? dynamic range is 87 db ? minimum rssi value is 0 ? maximum rssi value is 28 8.3.1 overview the rssi is a 5 - bit value indicating the receive power in the selected channel , in steps of 3 db . no attempt is made to distinguish ieee 802.15.4 signals from others, only the received signal strength is evaluated. the rssi provides the basis for an ed measurement, see section 8.4 . 8.3.2 reading rssi in basic operating mode the rssi value is valid in any receive state, and is updated every t rssi = 2 s to regis ter bits rssi (register 0x06 , phy_rssi). it is not recommended to read the rssi value when using the extended operating mode or smart receiving, see section 11.10.2.2 . the automatically generated ed value should be used alternatively, see section 8.4 . 8.3.3 data interpretation the rssi value is a 5 - bit value indicating the receive power, in steps of 3 db and with a range of zero to 28 . an rssi value of zero indicates a receiver rf input power of p rf - 91 db m. for an rssi value in the range of one to 28 , the rf input power can be calculated as follows: p rf [dbm] = rssi base_val + 3 x rssi figure 8 - 6 . mappin g between rssi value and received input power . -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 rssi receiver input power p rf [dbm] measured ideal
90 8351b C C AT86RF233 8.3.4 register description register 0x06 (phy_rssi): the phy_rssi register is a multi - purpose register that indicates fcs validity, to provide random numbers, and a rssi value. figure 8 - 7 . register phy_rssi. bit 7 6 5 4 0x06 rx_crc_valid rnd_value rssi phy_rssi read/write r r r r reset value 0 1 1 0 bit 3 2 1 0 0x06 rssi phy_rssi read/write r r r r reset value 0 0 0 0 ? bit 4:0 - rssi received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3db. table 8 - 9 . rssi. register bits value description rssi 0x00 minimum rssi value 0x1c maximum rssi value the result of the automated rssi measurement is stored in register bits rssi. the value is updated every t rssi = 2 s in receive states. the read value is a number between zero and 28 indicating th e received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3 db . an rssi value of zero indicates an rf input power of p rf - 91 d b m ( rssi base_val ), a value of 28 a power of p rf - 7 db m (see parameter rssi max specified in section 12.7 ).
91 8351b C C AT86RF233 8.4 energy detection (ed) the atmel AT86RF233 energy detection (ed) module is characterized by : ? 84 unique energy levels defined ? 1 db resolution ? a measurement time of eight symbol periods for ieee 802.15.4 compliant data rates 8.4.1 overview the receiver ed measurement (ed scan procedure) can be used as a part of a channel selection algorithm. it is an estimation of the received signal power within the bandwidth of an ieee 802.15.4 channel. no attempt is made to identify or decode signals on t he channel. the ed value is calculated by averaging rssi values over eight symbols (128 s ) . for high data rate modes the automated ed measurement duration is reduced to 32 s , refer to section 11.3 . for manually initiated ed measurements in these modes the measurement period is still 128 s as long as the receiver is in rx_on state. 8.4.2 measurement description there are two ways to initiate an ed measurement: ? manually, by writing an arbitrary value to register 0x 07 (phy_ed_level), or ? automatically, after detection of a valid shr of an incoming frame. manually: for manually initiated ed measurements, the radio transceiver needs to be either in the state rx_on or busy_rx. the end of the ed measurement time ( eight symbol periods plus a processing time ) is indicated by the interrupt irq_ 4 ( cca_ed_done ) and the measurement result is stored in register 0x07 (phy_ed_level), refer to t ed i n table 7 - 2 . in order to avoid interference with an automatically initiated ed measurement, the shr detection can be disabled by setting register bit r x_pdt_dis (re gister 0x15, rx_syn), refer to section 9.1 . note: 1. it is not recommended to manually initiate an ed measurement when using the extended operating mode. automatically: an automated ed measurement is started upon shr detection. the end of the automated measurement is not signaled by an interrupt. when using basic operating mode, a valid ed value from the currently received frame is accessible 108 s after irq_2 ( rx_start ) and remains valid until a new rx_start interrupt is generated by the next incoming frame or until another ed measurement is initiated. when using the extended operating mode, i t is recommended to mask irq_2 ( rx_start ) , thus the interrupt cannot be used as timing reference. a succ essful frame reception is signalized by interrupt irq_3 ( trx_end ) . the minimum time span between a n irq_3 ( trx_end ) interrupt and a following sfd detection is t shr_sync = 96 s due to the length of the shr . including the
92 8351b C C AT86RF233 ed measurement time, the ed value needs to be read within 224 s after the trx_end interrupt; otherwise, it could be overwritten by the result of the next measurement cycle . this is important for time critical applications or if interrupt irq_2 ( rx_start ) is not used to indicate the reception of a frame. note: 2. the ed result is not updated during the rest of the frame reception, even by requesting an ed measurement manually. 8.4.3 data interpretation the phy_ed_level is an 8 - bit register. the ed_level value of the atmel AT86RF233 has a valid range from 0 x00 to 0x5 3 with a resolution of 1 db . a value of 0xff indicates the reset value. all other values do not occur . due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ed_level value has a maximum tolerance of 5 db , this is to be considered as constant offset over the measurement range. an ed_level value of zero indicates an rf input power of p rf - 91 dbm (see parameter rssi base_val , section 12.7 ) . for an ed_level value in the range of one to 8 3 , the rf input power can be calculated as follows: p rf [dbm] = rssi base_val + ed_level figure 8 - 8 . mapping between received input power and ed value . 8.4.4 interrupt handling interrupt irq_ 4 ( cca_ed_done ) is issued at the end of a manually initiated ed measurement. note: 1. an ed request should only be initiated in receive states. otherwise the radio transceiver generates an irq_ 4 ( cca_ed_done ) ; however no ed measurement was performed. -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 10 20 30 40 50 60 70 80 90 phy_ed_level (register 0x07) receiver input power p rf [dbm] measured ideal
93 8351b C C AT86RF233 8.4.5 register description register 0x07 (phy_ed_level): the phy_ed_level register cont ains the result of an ed measurement. figure 8 - 9 . register phy_ed_level. bit 7 6 5 4 0x07 ed_level phy_ed_level read/write r r r r reset value 1 1 1 1 bit 3 2 1 0 0x07 ed_level phy_ed_level read/write r r r r reset value 1 1 1 1 ? bit 7:0 - ed_level the register bits ed_level signals the ed level for the current channel. table 8 - 10 . ed_level. register bits value description ed_level 0x00 minimum ed level value 0x53 maximum ed level value 0xff reset value the min imum ed value zero indicates receiver power less than or equal rssi base_val . the range is 8 3 db with a resolution of 1 db and an accuracy of 5 db . the value 0xff signals that no measurement has been started yet (reset value). a manual ed measurement can be initiated by a write access to the register. the measurement duration is eight symbol periods (128s ) for a data rate of 250 kb/s . for high data rate modes the automated measurement duration is reduced to 32 s , refer to section 11.3 . for manually initiated ed measurements in these modes the measurement period is still 128 s as long as the receiver is in rx_on state.
94 8351b C C AT86RF233 8.5 clear channel assessment (cca) the main features of the clear channel assessment (cca) module are: ? all four modes are available as defined by ieee 802.15.4 - 2006 in section 6. 9.9 ? adjustable threshold for energy detection algorithm 8.5.1 overview a cca measurement is used to detect a clear channel. four cca modes are specified by ieee 802.15.4 - 2006 : table 8 - 11 . cca mode overview . cca mode description 1 energy above threshold . cca shall report a busy medium upon detecting any energy above the ed threshold. 2 carrier sense only . cca shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an ieee 802.15.4 compliant signal . th e signal strength may be above or below the ed threshold. 0 , 3 carrier sense with energy above threshold . cca shall report a busy medium using a logical combination of - detection of a signal with the modulation and spreading characteristics of this standard and - energy above the ed threshold. where the logical operator may be configured as either or (mode 0) or and (mode 3) . 8.5.2 configuration and request the cca modes are configurable via register 0x 08 (phy_cc_cca). when being in basic operating mode, a n cca request can be initiated manually by setting cca_request = 1 ( register 0x 08 , phy_cc_cca), if the atmel AT86RF233 is in any rx state. the current channel status (cca_status) and the cca completion status (cca_done) are accessible thro ugh register 0x 01 (trx_status). the cca evaluation is done over eight symbol period s and the result is accessible t cca = 180 s (max.) ( 128 s measurement duration and processing delay ) after the request , refer to table 7 - 2 . the end of a manually initiated cca measurement is ind icated by an interrupt irq_ 4 ( cca_ed_done ) . the register bits cca_ed_thres of register 0x 09 (cca_thr es) defines the receive power threshold of the D energy above threshold algorithm. the threshold is calculated by rssi base_val + 2 x cca_ed_thres [db ]. any received power above this level is interpreted as a busy channel. note: 1. it is not recommended to manually initiate a n cca measurement when using the extended operating mode.
95 8351b C C AT86RF233 8.5.3 data interpretation the atmel AT86RF233 current channel status (cca_status) and the cca completion status (cca_done) are accessible through register 0x 01 (trx_status). note that register bits cca_done and cca_status are cleared in response to a n cca_request . the completion of a measurement cycle is indicated by cca_done = 1. if the radio transceiver detects no signal (idle channel) during the cca evaluation period, the cca_status bit is set to one ; otherwise, it is set to zero . when using the Denergy above threshold algorithm, any received power above cca_ed_thres level is in terpreted as a busy channel . the Dcarrier sense algorithm reports a busy channel when detecting an ieee 802.15.4 signal above the rssi base_val (see section 12.7 ). the radio transceiver is also able to detect signals below this value, but the detection probability decreases with the signal power. it is alm ost zero at the radio transceivers sensitivity level (see parameter p sens on section 12.7 ). 8.5.4 interrupt handling i nterrupt irq_ 4 ( cca_ed_done ) is issued at the end of a manually initiated cca measurement. note : 1. a cca request should only be initiated in basic operating mode receive states. otherwise the radio transceiver generates an irq_ 4 ( cca_ed_done ) and sets the register bit cca_done = 1, even though no cca measurement was p erformed. 8.5.5 measurement time the response time for a manually initiated cca measurement depends on the receiver state. in rx_on state the cca measurement is done over eight symbol period s and the result is accessible t cca = 180 s (max.) after the request (see above) . in busy_rx state the cca measurement duration depends on the cca mode and the cca request relative to the reception of an shr. the end of the cca measurement is indicated by an irq_ 4 ( cca_ed_done ) . the variation of a cca measurement period in busy_rx state is described in table 8 - 12 . it is recommended to perform cca measurements in rx_on state only. to avoid switching accidentally to busy_rx state the shr detection can be disabled by setting register bit rx_pdt_dis (register 0x15, rx_syn), refer to section 9.1 . the receiver remains in rx_on state to perform a cca measurement until the register bit rx_pdt_dis is set back to continue the frame reception. in this case the cca measure ment duration is eight symbol periods. table 8 - 12 . cca measurement period and access in busy_ r x state . cca mode request within ed measurement (1) request after ed measurement 1 energy above threshold . cca result is available after finishing automated ed measurement period. cca result is immediately available after request. 2 carrier sense only . cca result is immediately available after request.
96 8351b C C AT86RF233 cca mode request within ed measurement (1) request after ed measurement 3 carrier sense with energy above threshold (and) . cca result is available after finishing automated ed measurement period. cca result is immediately available after request. 0 carrier sense with energy above threshold (or) . cca result is available after finishing automated ed measurement period. cca result is immediately available after request. note: 1. after receiving the shr an automated ed measureme nt is started with a length of eight symbol periods (psdu rate 250 kb/s) , refer to section 8.4 . this automated ed measurement must be finished to provide a result for the cca measurement. only one automated ed measurement per frame is performed. 8.5.6 register description register 0x01 (trx_status): the read - only register trx_status signals the present state of the radio transceiver as well as the status of a cca operation. figure 8 - 10 . register trx_status. bit 7 6 5 4 0x01 cca_done cca_status reserved trx_status trx_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x01 trx_status trx_status read/write r r r r reset value 0 0 0 0 ? bit 7 - cca_done table 8 - 13 . cca_done. register bits value description cca_done 0 cca calculation not finished 1 cca calculation finished the register bit cca_done indicates if a cca request is completed. this is also indicated by an interrupt irq_ 4 ( cca_ed_done ) . the register bit cca_done is cleared in response to a cca_request. ? bit 6 - cca_status table 8 - 14 . cca_status. register bits value description cca_status 0 channel indicated as busy 1 channel indicated as idle after a cca request is completed , the result of the cca measurement is available in register bit cca_status. the register bit cca_status is cleared in response to a n cca_request.
97 8351b C C AT86RF233 register 0x08 (phy_cc_cca): the phy_cc_cca register is a multi - purpose register that controls cca configurat ion, cca measurement, and the ieee 802.15.4 channel setting. figure 8 - 11 . register phy_cc_cca. bit 7 6 5 4 0x08 cca_request cca_mode channel phy_cc_cca read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x08 channel phy_cc_cca read/write r/w r/w r/w r/w reset value 1 0 1 1 ? bit 7 - cca_request the register bit cca_request initiates a manual started cca measurement. table 8 - 15 . cca_request. register bits value description cca_request 0 reset value 1 starts a cca measurement notes: 1. the read value returns always with zero. 2. if a cca request is initiated in states others than rx_on or rx_busy the phy generates an irq_4 (cca_ed_done) and sets the register bit cca_done, however no cca was carried out. a manual cca measurement is initiated with setting cca_request = 1. the end of the cca measurement is indicated by interrupt irq_ 4 ( cca_ed_done ) . register bits cca_done and cca_status ( register 0x 01, trx_status) are updated after a cca_request. the register bit is automatically cleared after requesting a cca measurement with cca_request = 1. ? bit 6:5 - cca_mode the cca mode can be selected using register bits cca_mode. table 8 - 16 . cca_mode. register bits value description cca_mode 0 mode 3a, carrier sense or energy above threshold 1 mode 1, energy above threshold 2 mode 2, carrier sense only 3 mode 3b, carrier sense and energy above threshold note: 1. ieee 802.15.4 C 2006 cca mode 3 defines the logical combination of cca mode 1 and 2 with the logical operators and or or.
98 8351b C C AT86RF233 register 0x09 (cca_thres): the cca_thres register sets the ed threshold level for cca. figure 8 - 12 . register cca_thres. bit 7 6 5 4 0x09 reserved cca_thres read/write r/w r/w r/w r/w reset value 1 1 0 0 bit 3 2 1 0 0x09 cca_ed_thres cca_thres read/write r/w r/w r/w r/w reset value 0 1 1 1 ? bit 3:0 - cca_ed_thres an ed value above the threshold signals the channel as busy during a cca_ed measurement. table 8 - 17 . cca_ed_thres. register bits value description cca_ed_thres 0x7 for cca_mode = 1, a busy channel is indicated if the measured received power is above p_thres [dbm] = rssi_base_val + 2[db] x cca_ed_thres. cca modes 0 and 3 are logically related to this resu lt.
99 8351b C C AT86RF233 8.6 link quality indication (lqi) the ieee 802.15.4 standard defines the lqi as a characterization of the strength and/or quality of a received frame. the use of the lqi result by the network or application layer is not specified in this standard. the l qi value shall be an integer rangin g from zero to 255, with at least eight unique values. the minimum and maximum lqi values ( 0x00 and 0xff ) should be associated with the lowest and highest quality compliant signals, respectively, and lqi values in between should be uniformly distributed between these two limits. 8.6.1 overview the lqi measurement of the atmel AT86RF233 is implemented as a measure of the link quality which can be described with the packet error rate (per ) for this link. an lqi value can be associated with an expected packet error rate. the per is the ratio of erroneous received frames to the total number of received frames. a per of zero indicates no frame error, whereas at a per of one no frame was recei ved correctly. the radio transceiver uses correlation results of multiple symbols within a frame to determine the lqi value. this is done for each received frame. the minimum frame length for a valid lqi value is two octets psdu. lqi values are integers ranging from zero to 255. as an example, figure 8 - 13 shows the conditional packet error rate (per) when receiving a certain lqi value. figure 8 - 13 . conditional packet error rate versus lqi . that means that a large number of transmission with an identical lqi value results in a packet error rate shown in the figure 8 - 13 . lost packets have been discarded since in this case there is no lqi value available. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 50 100 150 200 250 per lqi
100 8351b C C AT86RF233 if, instead, the mean lqi over a large number of transmissions is computed, and the mean lqi is quantized to an lqi value of the figure, the corresponding frame error rate is not strictly equal to the true error rate. the values are taken from received frames of psdu length of 20 octets on transmission channels with reasonable low multipath delay sp reads. i f the transmission channel characteristic has higher multipath delay spread than assumed in the example, the pe r is slightly higher for a certain lqi value . since the packet error rate is a statistical value, the per shown in figure 8 - 13 is based on a huge number of transactions . a reliable estimation of the packet error rate cannot be based on a single or a small number of lqi values. 8.6.2 obtaining the lqi value the lqi value can be obtained after a frame has been received by the radio transceiver. one additional byte is automatically attached to the received frame containing the lqi value. this information can also be read via frame buffer read acce ss, see section 6.3.2 . the lqi byte can be read after irq_3 ( trx_end ) interrupt. 8.6.3 data interpretation according to ieee 802.15.4 a low lqi value is associated with low signal strength and/or high signal distortions. signal distortions are ma i nly caused by in terference signals and/or multipath propagation. high lqi values indicate a sufficient high signal power and low signal distortions. note: 1. the received signal power as indicated by received signal strength indication (rssi) value or energy detection (ed) v alue of the atmel AT86RF233 do not characterize the signal quality and the ability to decode a signal. as an example, a received signal with an input power of about 6 db above the receiver sensitivity likely results in a lqi value close to 255 for radio channels with very low signal distortions. for higher signal power the lqi value becomes independent of the actual signal strength. this is because the packet error rate f or these scenarios tends towards zero and further increas ed signal strength, that is increasing the transmission power does not decrease the error rate any further. in this case rssi or ed can be used to evaluate the signal strength and the link margin. zi gbee networks often require the identification of the Dbest routing between two nodes. both, the lqi and the rssi/ed can be used for this, depend ent on the optimization criteria. if a low packet error rate (corresponding to high throughput) is the optimization criteria then the lqi value should be taken into consideration. if a low transmission power or the link margin is the optimization criteria then the rssi/ed value is also hel pful. combinations of lqi, rssi and ed are possible for routing decisions. as a rule of thumb rssi and ed values are useful to differentiate between links with high lqi values. transmission links with low lqi values should be discarded for routing decision s even if the rssi/ed values are high. this is because rssi/ed does not say anything about the possibility to decode a signal. it is only an information about the received signal strength whereas the source can be an interferer.
101 8351b C C AT86RF233 9 module description 9.1 receiver (rx) 9.1.1 overview the atmel AT86RF233 receiver is split into an analog radio front - end and a digital base band processor (rx bbp), see figure 9 - 1 . figure 9 - 1 . receiver block diagram . the differential rf signal is amplified by a low noise amplifier (lna), filtered (ppf) and down converted to an intermediate frequency by a mixer. channel selectivity is performed using an integrated band pass filter (bpf) . a limiting amplifier (limiter) provides sufficient gain to overcome the dc offset of the succeeding analog - to - digital c onverter (adc) and generates a digital rssi signal. the adc output signal is sampled and processed further by the digital base band receiver (rx bbp) . the rx bbp performs additional signal filtering and signal synchronization. the frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. the receiver is designed to handle frequency and symbol rate deviations f srd up to 12 0 ppm , caused by combined receiver and transmitter deviations. for details refer to section 12.5 parameter f srd . finally the signal is demodulated and the data are stored in the frame buffer. in basic operating mode , refer to section 7.1 , the reception of a frame is indicated by an interrupt irq_2 ( rx_start ) . accordingly its end i s signalized by an interrupt irq_3 ( trx_end ) . based on the quality of the received signal a link quality indicator (lqi) is calculated and appended to the fra me, refer to section 8.6 . additional signal processing is applied to the frame data to provide further status information like ed value ( register 0x 07, phy_ ed_level ) and fcs correctness ( register 0x 06, phy_rssi ). bey ond these features the extended operating mode of the AT86RF233 supports address filtering and pending data indication. for details refer to section 7.2 . 9.1.2 frame receive procedure the frame receive procedure including the radio transceiver setup for reception and reading psdu data from the frame buffer is described in section 10.1 frame receive procedure . 9.1.3 configuration in basic operating mode the receiver is enabled by writing command rx_on to register bits trx_cmd ( register 0x 02, trx_state) in states trx_off or pll_on. similar ly in extended operating mode, the receiver is enabled for rx_aack operation lna ppf bpf limiter adc agc rssi rfp rfn analog domain digital domain spi rx bbp frame buffer lo control , registers spi i / f c i / f
102 8351b C C AT86RF233 from state s trx_of f , pll_on or tx_aret_on by writing the command rx_aack_on. there is no additional configuration required to receive ieee 802.15.4 compliant frames when using the basic operating mode. however , the frame reception in the atmel AT86RF233 extended operating mode requires further register configurations, for details refer to section 7.2 . the AT86RF233 receiver has an outstanding sensitivity performance of - 101 dbm . at certain environmental conditions or for high data rate modes, refer to section 11.3 , it may be useful to manually decrease this sensitivity. this is achieved by adjusting the synchronization header detector threshold using register bits rx_pdt_level ( register 0x 15, rx_syn). received signals with an rssi value below the threshold do not activate the demodulation process. fu rther more , it may be useful to protect a received frame against overwriting by subsequent received frames. a dynamic frame buffer protection is enabled with register bit rx_safe_mode ( register 0x 0c, trx_ctrl_2) set, see section 11.8 . the receiver remains in rx_on or rx_aack_on state until the whole frame is uploaded by the microcontroller, indicated by pin 23 ( /sel ) = h during the spi frame receive mode. the frame buffer content is only protected if the fcs is valid. a static frame buffer protection is enabled with register bit rx_pdt_dis ( register 0x 15, rx_syn) set. the receiver remains in rx_on or rx_aack_on state and no further shr is detected until the register bit rx _pdt_dis is set back. 9.1.4 register description register 0x15 (rx_syn): the register rx_syn controls the blocking of receiver path and the sensitivity threshold of the receiver. figure 9 - 2 . register rx_syn. bit 7 6 5 4 0x15 rx_pdt_dis reserved rx_syn read/write r/w r r r reset value 0 0 0 0 bit 3 2 1 0 0x15 rx_pdt_level rx_syn read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 - rx_pdt_dis the register bit rx_pdt_dis prevents the reception of a frame during rx phase. table 9 - 1 . rx_pdt_dis. register bits value description rx_pdt_dis 0 rx path is enabled 1 rx path is disabled rx_pdt_dis = 1 prevents the reception of a frame even if the radio transceiver is in receive modes . an ongoing frame reception is not affected. this operation mode is independent of the settin g of register bits rx_pdt_level.
103 8351b C C AT86RF233 ? bit 3:0 - rx_pdt_level the register bits rx_pdt_level desensitize the receiver in steps of 3db. table 9 - 2 . rx_pdt_level. register bits value description rx_pdt_level 0x00 maximum rx sensitivity 0x0f rx input level > rssi_base_val + 3[db] x 14 t hese register bits desensitize the receiver such that frames with an rssi level below the rx_pdt_level threshold level (if rx_pdt_level > 0) are not received. for a rx_pdt_level > 0 value t he threshold level can be calculated according to the following formula: p rf [dbm] > rssi base_val + 3 x ( rx_pdt_level - 1) . examples for cer tain register settings are given in table 9 - 3 . table 9 - 3 . receiver desensitization threshold level C rx_pdt_level . register value rx input threshold level value [dbm] 0x0 rssi_base_val (reset value) rssi value not considered 0x1 > rssi_base_val + 3 ? 0 > - 9 1 0xe > rssi_base_val + 3 ? 1 3 > - 5 2 0xf > rssi_base_val + 3 ? 14 > - 4 9 if register bits rx_pdt_level = 0 (reset value) all frames with a valid shr and phr are received, independently of their signal strength. if register bits rx_pdt_level > 0 , the current consumption of the receiver in all rx lis ten ing states is reduced to i rx_on_l0 = 11.3 ma (typ.) , refer to section 12.8 . additional power saving techniques in receive modes are specified in section 11.10 .
104 8351b C C AT86RF233 9.2 transmitter (tx) 9.2.1 overview the atmel AT86RF233 transmitter consists of a digital base band processor (tx bbp) and an analog radio front end, see figure 9 - 3 . figure 9 - 3 . transmitter block diagram . the tx bbp reads the frame data from the frame buffer and performs the bit - to - symbol and symbol - to - chip mapping as specified by ieee 802.15.4 in section 6.5.2. the o - qpsk modulation signal is generated and f ed into the analog radio front end. the fractional - n frequency synthesizer (pll) converts the baseband transmit signal to the rf signal, which is amplified by the power amplifier (pa). the pa output is internally connected to bidirectional differential antenna pins (rfp, rfn), so that no ext ernal antenna switch is needed. 9.2.2 frame transmit procedure the frame transmit procedure including writing psdu data in the frame buffer and initiating a transmission is described in section 10.2 . 9.2.3 configuration the maximum output power of the transmitter is typical ly +4 dbm . the output power can be configured via register bits tx_pwr ( register 0x 05, phy_tx_pwr). the output power of the transmitter can be controlled over a range of 21 db . a transmission can be started from pll_on or tx_aret_on state by a rising edge of pin 11 ( slp_tr ) or by writing tx_start command to register bits trx_cmd ( register 0x 02, trx_state). figure 9 - 4 . tx power ramping for maximum tx power . pll C tx modulation pa ext . rf front - end and output power control spi i / f dig 3 / 4 rfp rfn tx data analog domain digital domain tx bbp frame buffer control , registers spi c i / f buf 0 6 8 1 0 t r x _ s t a t e s l p _ t r p l l _ o n 2 1 2 1 4 1 6 1 8 l e n g t h [ s ] p a b u f f e r 4 p a m o d u l a t i o n 1 1 0 0 0 0 0 0 1 b u s y _ t x 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1
105 8351b C C AT86RF233 9.2.4 tx power ramping to optimize the output power spectral density (psd), the pa buffer and pa are enabled sequentially , see in figure 9 - 4 . in this exampl e the transmission is initiated with the rising edge of pin 11 (slp_tr). the radio transceiver state changes from pll_on to busy_tx. the modulation of the frame starts 16 s after pin 11 (slp_tr) rising edge . 9.2.5 register description register 0x05 (phy_tx_pwr): the phy_tx_pwr register controls the output power of the transmitter. figure 9 - 5 . register phy_tx_pwr. bit 7 6 5 4 0x05 reserved phy_tx_pwr read/write r r/w r r reset value 0 0 0 0 bit 3 2 1 0 0x05 tx_pwr phy_tx_pwr read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 3:0 C tx_pwr the register bits tx_pwr determine the tx output power of the radio transceiver. table 9 - 4 . tx o utput p ower . register bits value tx output power [dbm] tx_pwr 0x0 +4 0x1 +3.7 0x2 +3.4 0x3 +3 0x4 +2.5 0x5 +2 0x6 +1 0x7 0 0x8 - 1 0x9 - 2 0xa - 3 0xb - 4 0xc - 6 0xd - 8 0xe - 12 0xf - 17
106 8351b C C AT86RF233 note: 1. a state change that is a command gets written to the trx_cmd field resets the value of the tx_pwr fields to the originally set value. 2. if the extended operating mode is used with rpc enabled (that is xah_tx_rpc_en is set to one), the read value of the tx_pwr field provides the used transmit power for last transmitted frame including acknowledgement frame. the tx_pwr field contains only th e value of the rpc - controlled transmission if a frame has already been sent. this allows monitoring the actual rpc handling used for transmitting.
107 8351b C C AT86RF233 9.3 frame buffer the atmel AT86RF233 contains a 128 byte dual port sram. one port is connected to the spi interface, the other one to the internal transmitter and receiver modules. for data communication, both ports are independent and simultaneously accessible. the frame buffer utilizes the sram address sp ace 0x00 to 0x7f for rx and tx operation of the radio transceiver and can keep a single ieee 802.15.4 rx or a single tx frame of maximum length at a time. frame buffer access modes are described in section 6.3.2 . frame buffer access conflicts are indicated by an under run interrupt irq_6 ( trx_ur ) . note: 1. t he irq_6 ( trx_ur ) interrupt also occurs on the attempt to write frames longer than 127 octets to the frame buffer (overflow) . in that case the content of the frame buffer cannot be guaranteed. frame buffer access is only possible if the digital voltage regulator (dvreg) is turned on. this is valid in all device states except in sleep or deep_sleep state. an access in p_on sta te is possible if pin 17 (clkm) provides the 1 mhz master clock. 9.3.1 data management data in frame buffer (received data or data to be transmitted) remains valid as long as: ? no new frame or other data are written into the buffer over spi ? no new frame is received (in any busy_rx state) ? no state change into sleep or deep_sleep state is made ? no reset took place by default there is no protection of the frame buffer against overwriting. therefore, if a frame is received during frame buffer rea d access of a previously received frame, interrupt irq_6 ( trx_ur ) is issued and the stored data might be overwritten. even so, the old frame data can be read, i f the spi data rate is higher than the effective over air data rate. for a data rate of 250 kb/s a minimum spi clock rate of 1 mhz is recommended. finally the microcontroller should check the transferred frame data integrity by a n fcs check. to protect the f rame buffer content against being overwritten by newly incoming frames , the radio transceiver state should be changed to pll_on state after reception. this can be achieved by writing immediately the command pll_on to register bits trx_cmd ( register 0x 02, t rx_state) after receiving the frame , indicated by irq_3 ( trx_end ) . alternatively , dynamic frame buffer protection can be used to protect received frames against overwriting, for details refer to section 11.8 . both procedures do not protect the frame buffer from overwriting by the microcontroller. in extended operating mode during tx_aret operation, see section 7.2.4 , the radio transceiver switches to receive, if an acknowledgement of a previously transmitted frame was requested. during this period received frames are evaluated, but not stored in the frame buffer. this allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing them again. a radio transceiver state change, except a transition to sleep , deep_sleep, or reset state , does not a ffect the frame buffer contents. if the radio transceiver is
108 8351b C C AT86RF233 forced into sleep or deep_sleep , the frame buffer is powered off and the stored data gets lost. 9.3.2 user accessible frame content the atmel AT86RF233 supports an ieee 802.15.4 compliant frame format as shown in figure 9 - 6 . figure 9 - 6 . AT86RF233 frame structure . note: 1. stored into frame buffer during frame reception. a frame comprises two sections, the radio transceiver internally generated shr field and the user accessible part stored in the frame buffer. the shr contains the preamble and the sfd field. the variable frame section contains the phr and the psdu includin g the fcs, see section 8.2 . to access the data follow the procedures described in section 6.3.2 . the frame length information (phr field) and the psdu are stored in the frame buffer. during frame reception, the link quality indicator (lqi) value, the energy detection (ed) value, and the status information (rx_status) of a received frame are additionally stored, see section 8.6 , section 8.4 , and section 6.3.2 , respectively. t he radio transceiver appends these values to the frame data during frame buffer read access. if the sram read access is used to read an rx frame, the frame length field (phr) can be accessed at address zero . the shr (except the sfd value used to generate t he shr) cannot be read by the microcontroller. for frame transmission, the phr and the psdu needs to be stored in the frame buffer. the maximum frame buffer size supported by the radio transceiver is 128 bytes. if the register bit tx_auto_crc_on is set in register 0x 05 (phy_tx_pwr), the fcs field of the psdu is replaced by the automatically calculated fcs during frame transmission. there is no need to write the fcs field when using the automatic fcs generation. to manipulate individual bytes of the frame bu ffer a sram write access can be used instead. for non ieee 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte (frame length field + one byte of data). 9.3.3 interrupt handling access conflicts may occur when reading and writing data simultaneously at the two independent ports of the frame buffer, tx/rx bbp and spi. these ports have their own address counter that points to the frame buffers current address. access violations occ urs during concurrent frame buffer read or write accesses, when the spi ports address counter value becomes higher than or e qual to that of tx/rx bbp port. p r e a m b l e s e q u e n c e s f d p h r p a y l o a d l q i ( 1 ) f c s 0 4 5 6 n + 3 n + 5 n + 6 f r a m e a c c e s s s h r n o t a c c e s i b l e r x : f r a m e b u f f e r c o n t e n t p h y g e n e r a t e d l e n g t h [ o c t e t s ] d u r a t i o n 4 o c t e t s 1 n o c t e t s ( n < = 1 2 8 ) 3 o c t e t s t x : f r a m e b u f f e r c o n t e n t e d ( 1 ) r x _ s t a t u s ( 1 ) n + 7 n + 8
109 8351b C C AT86RF233 while receiving a frame, primarily the data needs to be stored in the frame buffer before reading i t. this can be ensured by accessing the frame buffer 32 s after irq_2 ( rx_start ) at the earliest. when reading the frame data continuously the spi data rate shall be lower than 250 kb/s to ensure no under run interrupt occurs. to avoid access conflicts and to simplify the frame buffer read access frame buffer empty indication may be used, for details refer to section 11.7 . during transmission, an access violation occurs on frame buffer write access , when the spi ports address counter value becomes less than o r equal to that of tx bbp port. both these access violations may cause data corruption and are indicated by irq_6 ( trx_ur ) interrupt when using the frame buffer access mode. access violations a re not indicated when using the sram a ccess mode . notes: 1. interrupt irq_6 ( trx_ur ) is valid 64 s after irq_2 ( rx_start ) . the occurrence of the interrupt can be disregarded when reading the first byte of the frame buffer between 32 s and 64 s after the rx_start interrupt. 2. if a frame buffer read access is not finished until a new frame is received, an irq_6 ( trx_ur ) interrupt occurs. nevertheless the old frame data can be read, if the spi data rate is higher than the effective phy data rate. a minimum spi clock rate of 1 mhz is recommended in this case. finally, the microcontroller should check the integrity of the transferred frame data by calculating the fcs. 3. when writing data to the frame buffer during frame transmission, the spi data rate shall be higher than the phy data rate to ensure no under run interrupt. the first byte of the psdu data must be available in the frame buffer before sfd transmission is com plete, which takes 176 s ( 16 s pa ramp - up + 160 s shr) from the rising edge of pin 11 ( slp_tr ) (see figure 7 - 2 ) .
110 8351b C C AT86RF233 9.4 voltage regulators (avreg, dvreg) the main features of the voltage regulator blocks are: ? bandgap stabilized 1.8v supply for analog and digital domain ? low dropout (ldo) voltage regulator ? configurable for usage of an external voltage regulator 9.4.1 overview the internal voltage regulators supply a stabilized voltage to the atmel AT86RF233 . the avreg provides the regulated 1.8v supply voltage for the analog section and the dvreg supplies the 1.8v supply v oltage for the digital section. a simplified schematic of the internal voltage regulator is shown in figure 9 - 7 . figure 9 - 7 . simplified schematic of avreg/dvreg . the voltage regulators require bypass capacitors for stable operation. the va lue of the bypass capacitors determine the settling time of the voltage regulators. the bypass capacitors shall be placed as close as possible to the pins and shall be connected to ground with the shortest possible traces. 9.4.2 configur ation the voltage regulators can be configured by the register 0x 10 (vreg_ctrl). it is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external voltage supply . for this configuration, the internal regul ators need to be switched off by setting the register bits to the values avreg_ext = 1 and dvreg_ext = 1. a regulated external supply voltage of 1.8v needs to be connected to the pins 13, 14 ( dvdd ) and pin 29 ( avdd ) . when turning on the external supply, en sure a sufficiently long stabilization time before interacting with the AT86RF233 . 9.4.3 data interpretation the status bit s avdd_ok = 1 and dvdd_ok = 1 of register 0x 10 (vreg_ctrl) indicate an enabled and stable intern al supply voltage. reading value zero indicates a disabled or internal supply voltage not settled to the final value . setting avreg_ext = 1 and dvreg_ext = 1 forces the signals avdd_ok and dvdd_ok to one . bandgap voltage reference 1 . 25 v avdd , dvdd ( d ) evdd
111 8351b C C AT86RF233 9.4.4 register description register 0x10 (vreg_ctrl): the vreg_ctrl register controls the use of the voltage regulators and indicates the status of these. figure 9 - 8 . register vreg_ctrl. bit 7 6 5 4 0x10 avreg_ext avdd_ok reserved vreg_ctrl read/write r/w r r r reset value 0 0 0 0 bit 3 2 1 0 0x10 dvreg_ext dvdd_ok reserved vreg_ctrl read/write r/w r r r reset value 0 0 0 0 ? bit 7 - avreg_ext if set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8v supply for the analog building blocks. table 9 - 5 . avreg_ext. register bits value description avreg_ext 0 internal voltage regulator enabled, analog section 1 internal voltage regulator disabled, use external regulated 1.8v supply voltage for the analog section ? bit 6 - avdd_ok this register bit indicates if the internal 1.8v regulated voltage supply avdd has settled. the bit is set to logic high, if avreg_ext = 1. table 9 - 6 . avdd_ok. register bits value description avdd_ok 0 analog voltage regulator is disabled or supply voltage not stable 1 analog supply voltage has been settled ? bit 3 - dvreg_ext if set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8v supply for the digital building blocks. table 9 - 7 . dvreg_ext. register bits value description dvreg_ext 0 internal voltage regulator enabled, digital section 1 internal voltage regulator disabled, use external regulated 1.8v supply voltage for the digital section
112 8351b C C AT86RF233 ? bit 2 - dvdd_ok this register bit indicates if the internal 1.8v regulated voltage supply dvdd has settled. the bit is set to logic high, if dvreg_ext = 1. table 9 - 8 . dvdd_ok. register bits value description dvdd_ok 0 digital voltage regulator is disabled or supply voltage not stable 1 digital supply voltage has settled note: 1. while the reset value of this bit is zero, any practical access to the register is only possible when dvreg is active. so this bit is normally always read out as one.
113 8351b C C AT86RF233 9.5 battery monitor (batmon) the main features of the battery monitor are: ? configurable v oltage threshold from 1.7 0 v to 3.675v ? generation of an interrupt when supply voltage drops below the threshold ? current state can be monitored in a register bit 9.5.1 overview the atmel AT86RF233 battery monitor (batmon) detects and indicates a low supply voltage of the external supply voltage at pin 2 8 (evdd) . this is done by comparing the voltage on the external supply pin 28 (evdd) with a configurable internal threshold voltage. a simplified schematic of the batmon wit h the most important input and output signals is shown in figure 9 - 9 . figure 9 - 9 . simplified schematic of batmon . 9.5.2 configur ation the batmon can be configured using the register 0x11 (batmon). register bits batmon_vth sets the threshold voltage. it is configurable with a resolution of 75 mv in the upper voltage range (batmon_hr = 1) and with a resolution of 50 mv in the lower voltage r ange (batmon_hr = 0), for details refer to register 0x11 (batmon). 9.5.3 data interpretation the signal register bit batmon_ok of register 0x11 (batmon) monitors the current value of the battery voltage: ? if batmon_ok = 0, the battery voltage is lower than the th reshold voltage ? if batmon_ok = 1, the battery voltage is higher than the threshold voltage after setting a new threshold, the value batmon_ok should be read out to verify the current supply voltage value. note: 1. the battery monitor is inactive during p_on, sleep, and deep_sleep states, see register bits trx_status (register 0x01, trx_status). batmon _ hr batmon _ vth 4 evdd threshold voltage batmon _ ok ? 1 D batmon _ irq for input - to - output mapping see control register 0 x 11 ( batmon ) dac + - d q clear
114 8351b C C AT86RF233 9.5.4 interrupt handling a supply voltage drop below the configured threshold value is indicated by an interrupt irq_7 ( bat_low ) , see section 6.7 . note: 1. the atmel AT86RF233 irq_7 ( bat_low ) interrupt is issued only if batmon_ok changes from one to zero . no interrupt is generated when: ? the battery voltage is under the default 1.8v threshold at power - on (batmon_ok was never one ), or ? a new threshold is set, which is still above the current supply voltage (batmon_ok remains zero ). when the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. to avoid th is: ? disable the irq_7 ( bat_low ) in register 0x 0e (irq_mask) and treat the battery as empty, or ? set a lower threshold value. 9.5.5 register description register 0x11 (batmon): the batmon register configures the battery monitor to compare the supply voltage at pin 28 (evdd) to the threshold. additionally, the supply voltage status at pin 28 (evdd) can be read from register bit batmon_ok according to the actual batmon se ttings. figure 9 - 10 . register batmon. bit 7 6 5 4 0x11 reserved batmon_ok batmon_hr batmon read/write r r/w r r/w reset value 0 0 0 0 bit 3 2 1 0 0x11 batmon_vth batmon read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 5 - batmon_ok the register bit batmon_ok indicates the level of the external supply voltage with respect to the programmed threshold batmon_vth. table 9 - 9 . batmon_ok. register bits value description batmon_ok 0 the battery voltage is below the threshold 1 the battery voltage is above the threshold
115 8351b C C AT86RF233 ? bit 4 - batmon_hr the register bit batmon_hr sets the range and resolution of the battery monitor. table 9 - 10 . batmon_hr. register bits value description batmon_hr 0 enables the low range, see batmon_vth 1 enables the high range, see batmon_vth ? bit 3:0 C batmon_vth the threshold values for the battery monitor are set by register bits batmon_vth . table 9 - 11 . battery monitor threshold voltages . value batmon_vth voltage [v] batmon_hr = 1 voltage [v] batmon_hr = 0 0x0 2.550 1.70 0x1 2.625 1.75 0x2 2.700 1.80 0x3 2.775 1.85 0x4 2.850 1.90 0x5 2.925 1.95 0x6 3.000 2.00 0x7 3.075 2.05 0x8 3.150 2.10 0x9 3.225 2.15 0xa 3.300 2.20 0xb 3.375 2.25 0xc 3.450 2.30 0xd 3.525 2.35 0xe 3.600 2.40 0xf 3.675 2.45
116 8351b C C AT86RF233 9.6 crystal oscillator (xosc) the main crystal oscillator features are: ? 16 mhz amplitude controlled crystal oscillator ? 180 s typical settling time after leaving sleep state ? 330 s typical settling time after leaving deep_sleep state ? configurable trimming capac itance array ? configurable clock output (clkm) 9.6.1 overview the crystal oscillator generates the reference frequency for the atmel AT86RF233 . all other internally generated frequencies of the radio transceiver are deri ved from this unique frequency. therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency. the external components of the crystal oscillator should be selected carefully and the related board layout shoul d be done with caution (see chapter 5 ). the register 0x 12 (xosc_ctrl) provides access to the control signals of the oscillator. two operating modes are supported. it is recommended to use the integrated oscillator setup as described in figure 9 - 11 . alternatively, a reference frequency can be fed to the internal circuitry by using an external clock reference as shown in figure 9 - 12 . 9.6.2 integrated oscillator setup using the internal oscillator, the oscillation frequency depends on the load capa citance between the crystal pin 26 ( xtal1 ) and pin 25 ( xtal2 ) . the total load capacitance c l must be equal to the specified load capacitance of the crystal itself. it consists of the external capacitors cx and parasitic capacitanc es connected to the xtal nodes. figure 9 - 11 shows all parasitic capacitances, such as pcb stray capacitances and the pin input capacitance, summarized to c par . figure 9 - 11 . simplified xosc schematic with external components . c x c x 1 6 m h z x t a l 2 x t a l 1 e v d d c t r i m c t r i m c p a r c p a r a t 8 6 r f 2 3 3 p c b x t a l _ t r i m [ 3 : 0 ] e v d d v d d x t a l _ t r i m [ 3 : 0 ]
117 8351b C C AT86RF233 additional internal trimming capacitors c trim are available. any value in the range from 0 pf to 4. 5 pf with a 0.3 pf resolution is selectable u sing xtal_trim of register 0x 12 (xosc_ctrl). to calculate the total load capacitance, th e following formula can be used c l [pf] = 0.5 x ( cx + c trim + c par ). the atmel AT86RF233 trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. note that the oscillation frequency can only be reduced by increasing the trimming capacitance. the frequency deviation caused by one step of c trim decreases with increasing crystal load capacitor values. a n amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal types. enabling the crystal os cillator in p_on state and after leaving sleep or deep_sleep state causes a slightly high er current during the amplitude build - up phase to guarantee a short start - up time. at stable operation, the current is reduced to the amount necessary for a robust operation. this also keeps the drive level of the crystal low. generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effect s caused by external component variations or by variations of board and circuit parasitic . on the other hand, a larger crystal load capacitance results in a longer start - up time and a higher steady state current consumption. 9.6.3 external reference frequency se tup when using an external reference frequency, the signal must be connected to pin 26 ( xtal1 ) as indicated in figure 9 - 12 and the register bits xtal_ mode ( register 0x 12 , xosc_ctrl) need to be set to the external oscillator mode for power saving reasons . the oscillation peak - to - peak amplitude shall be between 100 mv and 500 mv , the optimum range is between 400 mv and 500 mv . pin 25 (xtal2) should not be wired. it is possible, among other waveforms, to use sine and square wave signals. note: 1. the quality of the external reference (that is phase noise) determines the system performance. figure 9 - 12 . setup for using an external frequency reference . 9.6.4 master clock signal output (clkm) the generated reference clock signal can be fed to a microcontroller using pin 17 ( clkm ) . the internal 16 mhz raw clock can be divided by an internal prescaler. thus, clock frequencies of 16 mhz , 8 mhz , 4 mhz , 2 mhz , 1 mhz , 250 khz , or 62.5 khz can be supplied by pin 17 (clkm). the clkm frequency is configurable using register 0x 03 (trx_ctrl_0). there are two possibilities to change the clkm frequency. if clkm_sha_sel = 0, changing the x t a l 2 x t a l 1 a t 8 6 r f 2 3 3 p c b 1 6 m h z
118 8351b C C AT86RF233 register bits clkm_ctrl ( register 0x 03, trx_ctrl_0) immediately affects a glitch free the clkm clock rate change . otherwise (clkm_sha_sel = 1) the new clock rate is supplied when leaving the sleep state the next time. to r educed p ower c onsumption and spurious emissions, it is recommended to turn off the clkm clock when not in use . note s : 1. during reset procedure, see section 7.1.2.9 , register bits clkm_ctrl are shadowed. although the clock setting of clkm remains after reset, a read access to register bits clkm_ctrl delivers the reset value one . for that reason it is rec ommended to write the previous configuration (before reset) to register bits clkm_ctrl to align the radio transceiver behavior and register configuration. otherwise the clkm clock rate is set back to the reset value (1 mhz ) after the next sleep cycle . for e xample, if the clkm clock rate is configured to 16 mhz the clkm clock rate remains at 16 mhz after a reset, however the register bits clkm_ctrl are set back to one . sin ce clkm_sha_sel reset value is one , the clkm clock rate changes to 1 mhz after the next sle ep cycle if the clkm_ctrl setting is not updated. 2. after leaving the deep_sleep state clkm starts with the default 1 mhz master clock at pin 17 (clkm) after the crystal oscillator has stabilized. 9.6.5 register description register 0x03 (trx_ctrl_0): the trx_ctrl_0 register controls the clkm clock rate. figure 9 - 13 . register trx_ctrl_0. bit 7 6 5 4 0x03 reserved trx_ctrl_0 read/write r/w r r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x03 clkm_sha_sel clkm_ctrl trx_ctrl_0 read/write r/w r/w r/w r/w reset value 1 0 0 1 ? bit 3 - clkm_sha_sel the register bit clkm_sha_sel defines whether a new clock rate (defined by clkm_ctrl) is set immediately or gets effective after the next sleep cycle. table 9 - 12 . clkm_sha_sel. register bits value description clkm_sha_sel 0 clkm clock rate change appears immediately 1 clkm clock rate change appears after sleep cycle
119 8351b C C AT86RF233 ? bit 2:0 - clkm_ctrl the register bits clkm_ctrl set the clock rate of pin 17 (clkm). table 9 - 13 . clkm_ctrl. register bits value description clkm_ctrl 0 no clock at pin 17 (clkm), pin set to logic low 1 1mhz 2 2mhz 3 4mhz 4 8mhz 5 16mhz 6 250khz 7 62.5khz (ieee 802.15.4 symbol rate) note: 1. if a clock rate is selected between 1mhz and 16mhz and pin slp_tr is set to logic high in state trx_off, the trx delivers additional 35 clock cycles before entering state sleep or deep_sleep. register 0x12 (xosc_ctrl): the xosc_ctrl register controls the operation of the crystal oscillator. figure 9 - 14 . register xosc_ctrl. bit 7 6 5 4 0x12 xtal_mode xosc_ctrl read/write r/w r/w r/w r/w reset value 1 1 1 1 bit 3 2 1 0 0x12 xtal_trim xosc_ctrl read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:4 - xtal_mode the register bits xtal_mode sets the operating mode of the crystal oscillator. table 9 - 14 . xtal_mode. register bits value description xtal_mode 0x5 internal crystal oscillator disabled, use external reference frequency 0xf internal crystal oscillator enabled and xosc voltage regulator enabled all other values are reserved for normal operation the default value is set to xtal_mode = 0xf after reset. using an external clock source it is recommended to set xtal_mode = 0x 5 .
120 8351b C C AT86RF233 ? bit 3:0 - xtal_trim the register bits xtal_trim control internal capacitance arrays connected to pin 26 (xtal1) and pin 25 (xtal2). table 9 - 15 . xtal_trim. register bits value description xtal_trim 0x0 a capacitance value in the range from 0pf to 4.5pf is selectable with a resolution of 0.3pf. valid values are [0xf, 0xe, , 0x0].
121 8351b C C AT86RF233 9.7 frequency synthesizer (pll) the main pll features are: ? generate rx/tx frequencies for all ieee 802.15.4 C 2.4 ghz channels ? generate rx/tx frequencies from 2322 mhz to 2527 mhz ? autonomous calibration loops for stable operation within the operating range ? two pll - interrupts for status indication ? fast pll settling to support frequency hopping 9.7.1 overview the pll generates the rf frequencies for the atmel AT86RF233 . during receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency , during transmit operation the voltage - controlled oscillator (vco) is direct ly modulated to generate the rf transmit signal. the frequency synthesizer is imp lemented as a fractional - n pll. tw o calibration loops ensure correct pll functionality within the specified operating limits. 9.7.2 rf channel selection the pll is designed to support 16 channels in the 2. 4 ghz ism band with channel spacing of 5 mhz according to ieee 802.15.4 . the center frequency of these channels is defined as follows: fc [mhz] = 2405 + 5 x ( k C 11), for k = 11, 12, ..., 26 where k is the channel number. the channel k is selected by register bits channel ( register 0x 0 8 , phy_cc_ca). additionally, the pll supports all frequencies from 2322 mhz to 2527 mhz with 500 khz frequency spacing . the frequency is selected by cc_band (registers 0x14, cc_ctrl_1) and cc_number (registers 0x13, cc_ctrl_0). table 9 - 16 sho ws the settings of the regis ter bits cc_band and cc_number. table 9 - 16 . frequency bands and numbers . cc_band cc_number description 0x 0 not used channels according to ieee 802.15.4; frequency selected by register bits channel (register 0 x08, phy_cc_cca) 0x 1, , 0x 7 0 x00 C 0xff r eserved 0x 8 0x00 C 0x1f r eserved 0x 8 0x20 C 0xff 2322 mhz C 2433.5 mhz f c [mhz] = 2306 + 0.5 x cc_number 0x 9 0x00 C 0xba 2434 mhz C 2527 mhz . f c [mhz] = 2434 + 0.5 x cc_number 0x 9 0x bb C 0x ff r eserved 0xa , , 0xf 0x00 C 0xff r eserved
122 8351b C C AT86RF233 9.7.3 pll settling time and frequency agility when the pll is enabled during state transition from trx_off to pll_on , the settling time is typica lly t tr4 = 80 s , including settling of the analog voltage regulator (avreg) and pll self calibration, refer to table 7 - 2 and figure 13 - 14 . a lock of the pll is indicated with an interrupt irq_0 ( pll_lock ) . switching b etween 2.4 ghz ism band channels in pll_on or rx_on states is typically done within t pll_sw = 11 s . this makes the radio transceiver highly suitable for frequency hopping applications. when starting the transmit procedure the pll frequency is changed to the transmit frequency within a period of t rx_tx = 16 s before starting the transmission. after the transmission the pll settles back to the receive frequency within a period of t tx_rx = 32 s . t h is frequency step do es not generate an interrupt irq_0 ( pll_lock ) or irq_1 ( pll_unlock ) within these periods . 9.7.4 calibration loops due to variation of temperature, supply voltage and part - to - part variations of the radio transceiver the vco characteristics may vary. to ensure a stable operation , two automated control loops are implemented , center frequency (cf) tuning and delay cell (dcu) calibration . both calibration loops are initiated automatically when the pll is enabled during state transition from trx_off to pll_on or rx _on state . additionally, both calibration loops are initiated when the pll changes to a different frequency setting. if the pll operates for a long time on the same channel , for example more than five minutes , or the operating temperature changes significantly, it is recommended to initiate the calibration loops manually. both atmel AT86RF233 calibration loops can be initiated manually by spi command. to start the cali bration, the device should be in state pll_on. the center frequency calibration can be initiated by setting pll_cf_start = 1 (register 0x1a, pll_cf). the calibration loop is completed when the irq_0 ( pll_lock ) occurs , if enabled . the duration of the center frequency calibration loop depends on the difference between the current cf value and the final cf value. during the calibration, the cf va lue is incremented or decremented. each step takes t pll_cf = 8 s . the minimum time is 8 s ; the maximum time is 24 s . the recommended procedure to start the center frequency cali bration is to read the register 0x1a (pll_cf), to set th e pll_cf_start register bit to one , and to write th e value back to the register. the delay cell calibration can be initiated by setting th e bit pll_dcu_start of register 0x1b (pll_dcu) to one . the delay time of the programmable delay unit is adjusted to the correct value. the calibration works as successiv e approximation and is independen t of the values in the register 0x1b (pll_dcu). the duration of the calibration is t pll_dcu = 6 s . during both calibration processes, no correct receive or transmit operation is possible. the recommended state for the calibration is therefore pll_on, but calibration is not blocked at receive or transmit states. both calibrations can be executed concurre ntly.
123 8351b C C AT86RF233 9.7.5 interrupt handling t wo different interrupts indicate the pll status ( refer to register 0x 0f). irq_0 ( pll_lock ) indicates that the pll h as locked. irq_1 ( pll_unlock ) interrupt indicates an unexpected u nlock condition. a pll_lock interrupt clears any preceding pll_unlock i nterrupt automatically and vice versa. an irq_0 ( pll_lock ) interrupt is supposed to occur in the following situations: ? state change from trx_off to pll_on / rx_ on / tx_aret_on / rx_aack_on ? channel change in states pll_on / rx_ on / tx_aret_on / rx_aack_on any other occurrences of pll interrupts indicate erroneous behavior and require checking of the actual device status. th e state transition from busy_tx to pll_on after successful transmission do es not generate a n irq_0 ( pll_lock ) within the settling period . 9.7.6 r egister description register 0x08 (phy_cc_cca): the phy_cc_cca register is a multi - purpose register that controls cca configuration, cca measurement, and the ieee 802.15.4 channel setting. figure 9 - 15 . register phy_cc_cca. bit 7 6 5 4 0x08 cca_request cca_mode channel phy_cc_cca read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x08 channel phy_cc_cca read/write r/w r/w r/w r/w reset value 1 0 1 1 ? bit 4:0 C channel the register bit s channel define the rx/tx channel. the channel assignment is according to ieee 802.15.4. table 9 - 17 . c hannel assignment for ieee 802.15.4 C 2 .4 ghz b and . register bits value ieee 802.15.4 channel number k center frequency [mhz] channel 0x0b 11 2405 0x0c 12 2410 0x0d 13 2415 0x0e 14 2420 0x0f 15 2425 0x10 16 2430 0x11 17 2435 0x12 18 2440 0x13 19 2445
124 8351b C C AT86RF233 register bits value ieee 802.15.4 channel number k center frequency [mhz] 0x14 20 2450 0x15 21 2455 0x16 22 2460 0x17 23 2465 0x18 24 2470 0x19 25 2475 0x1a 26 2480 all other values are reserved register 0x13 (cc_ctrl_0): the cc_ctrl_0 register controls the frequency selection, if the selection by channel (register 0x08, phy_cc_cca) is not used. figure 9 - 16 . register cc_ctrl_0. bit 7 6 5 4 0x13 cc_number cc_ctrl_0 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x13 cc_number cc_ctrl_0 read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7:0 - cc_number table 9 - 18 . cc_number. register bits value description cc_number 0x00 alternative frequency selection with 500khz frequency spacing cc_band = 0x0: not used cc_band = 0x8: valid values are [0xff, 0xfe, , 0x20] cc_band = 0x9: valid values are [0xba, 0xb9, , 0x00] all other values are reserved
125 8351b C C AT86RF233 register 0x14 (cc_ctrl_1): the cc_ctrl_1 register controls the selection of the frequency bands. figure 9 - 17 . register cc_ctrl_1. bit 7 6 5 4 0x14 reserved cc_ctrl_1 read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x14 cc_band cc_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 3:0 - cc_band the register bits cc_band control the selection for ieee 802.15.4 channel band and additional frequencies bands. table 9 - 19 . cc_band. register bits value description cc_band 0x0 the ieee 802.15.4 channel within register bits channel is selected 0x8 the frequency band 0x8 is selected 0x9 the frequency band 0x9 is selected all other values are reserved if the register bits cc_band and cc_number are used, the frequency mapping is described in table 9 - 16 . register 0x1a (pll_cf): the pll_cf register controls the operation of the center frequenc y calibration loop. figure 9 - 18 . register pll_cf. bit 7 6 5 4 0x1a pll_cf_start reserved pll_cf read/write r/w r/w r/w r/w reset value 0 1 0 1 bit 3 2 1 0 0x1a pll_cf pll_cf read/write r/w r/w r/w r/w reset value 0 1 1 1
126 8351b C C AT86RF233 ? bit 7 - pll_cf_start manual start of center frequency calibration cycle. table 9 - 20 . pll_cf_start. register bits value description pll_cf_start 0 center frequency calibration cycle is finished 1 initiates center frequency calibration cycle pll_cf_start = 1 initiates the center frequency calibration. the calibration cycle has finished after t pll_cf = 8 s (typ.) . the register bit is cleared immediately after finishing the calibr ation. register 0x1b (pll_dcu): the pll_dcu register controls the operation of the delay cell calibration loop. figure 9 - 19 . register pll_dcu. bit 7 6 5 4 0x1b pll_dcu_start reserved pll_dcu read/write r/w r r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x1b reserved pll_dcu read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 7 - pll_dcu_start manual start of delay cell calibration cycle. table 9 - 21 . pll_dcu_start. register bits value description pll_dcu_start 0 delay cell calibration cycle is finished 1 initiates delay cell calibration cycle pll_ dcu _start = 1 initiates the delay cell calibration. t he calib ration cycle has finished after t pll_dcu = 6 s . the register bit is cleared immediately after finishing the calibration.
127 8351b C C AT86RF233 9.8 automatic filter tuning (ftn) 9.8.1 overview the atmel AT86RF233 ftn is incorporated to compensate device tolerances for temperature , supply voltage variations as well as part - to - part variations of the radio transceiver. the filter - tuning result is used to correct the analog baseband filter transfer function and the pll loop - filter time constant , refer to chapter 4 . a n ftn calibration cycle is initiated automatically when entering the trx_off state from the p_on, sleep, deep_sleep, or reset s tate . although receiver and transmitter are very robust against these variations , it is recommended to initiate the ftn manually if the radio transceiver does not use the sleep or deep_ sleep state s . if necessary, a calibration cycle is to be initiated in states trx_off, pll_on or rx_on . this applies in particular for the high data rate modes with a much higher sensitivity against bpf transfer function variations. the recommended calibration interval is five minutes or less. 9.8.2 register descripti on register 0x18 (ftn_ctrl): the ftn_ctrl register controls the operation of the filter tuning network calibration loop. figure 9 - 20 . register ftn_ctrl. bit 7 6 5 4 0x18 ftn_start reserved ftn_ctrl read/write r/w r/w r/w r/w reset value 0 1 0 1 bit 3 2 1 0 0x18 reserved ftn_ctrl read/write r/w r/w r/w r/w reset value 1 0 0 0 ? bit 7 - ftn_start manual start of a filter calibration cycle. table 9 - 22 . ftn_start. register bits value description ftn_start 0 filter calibration is finished 1 initiates filter calibration cycle ftn _start = 1 initiates the filter tuning network calibration. when the calibration cycle has finished after t ftn = 25 s (typ.). the register bit is cleared immediately after finishing the calibration.
128 8351b C C AT86RF233 10 radio transceiver usage this section describes basic procedures to receive and transmi t frames using the atmel AT86RF233 . for a detailed programming description refer to reference [ 7 ] . 10.1 frame receive procedure a frame reception comprises of two actions: the phy listens for, receives and demodulates the frame to the frame buffer and signalizes the reception to the microcontroller. after or during that process, the microcontroller can read the available frame data from the frame buffer via the spi interface. while being in state rx_on or rx_aack_on, the radio transceiver search es for incoming frames on the selected channel. assuming the appropriate interrupts are enabled, a detection of an ieee 802.15.4 compliant frame is indicated by interrupt irq_2 ( rx_start ) first . the frame reception is completed when issuing interrupt irq_3 ( trx_end ) . d ifferent frame buffer read access scenarios are recommended for : ? non - time critical applications read access starts after irq_3 ( trx_end ) ? time - critical applications read access starts after irq_2 ( rx_start ) for non - time - critical operations, it is recommended to wait for interrupt irq_3 ( trx_end ) before starti ng a frame buffer read access. figure 10 - 1 illustrates the frame receive procedure using irq_3 ( trx_end ) . figure 10 - 1 . transaction s between AT86RF233 and microcontroller during receive . critical protocol timing could require starting the frame buffer read access after interrupt irq_2 ( rx_start ) . the first byte of the frame data can be read 32 s after the irq_2 ( rx_start ) interrupt. the microcontroller must ensure to read slower than the frame is received. otherwise a frame b uffer under run occurs, irq_6 ( trx_ur ) is issued , and the frame data may be not valid. to avoid this, the frame buffer read access can be controlled by using a frame buffer empty indicator , refer to section 11.7 . a t 8 6 r f 2 3 3 m i c r o c o n t r o l l e r i r q i s s u e d ( i r q _ 2 ) r e a d i r q s t a t u s , p i n 2 4 ( i r q ) d e a s s e r t e d i r q i s s u e d ( i r q _ 3 ) r e a d f r a m e d a t a ( f r a m e b u f f e r a c c e s s ) r e a d i r q s t a t u s , p i n 2 4 ( i r q ) d e a s s e r t e d
129 8351b C C AT86RF233 10.2 frame transmit procedure a frame transmission comprises of two actions, a frame buffer write access and the transmission of the frame buffer content. both actions can be run in parallel if required by critical protocol timing. figure 10 - 2 illustrates the atmel AT86RF233 frame transmit procedure, when writing and transmitting the frame consecutively. after a frame buffer write access, the frame transmission is initiated by asserting pin 11 (slp_tr) or writing comm a nd tx_start to register bits trx_cmd (register 0x 02 , trx_state), while the radio transceiver is in state pll_on or tx_aret_on . the completion of the transaction is indicated by interrupt irq_3 ( trx_end ) . figure 10 - 2 . transaction between AT86RF233 and microcontroller during transmit . alternatively , a frame transmission can be started first , followed by the frame buffer write access (psdu data) ; refer to figure 10 - 3 . this is applicable for time critical applications. initiating a transmis sion, either by asserting pin 11 ( slp_tr ) or command tx_start to register bits trx_cmd ( register 0x 02, trx_state), the radio transceiver starts transmitting the shr , which is internally generated . this first phase requires 16 s for pll settling and 160s for shr tra nsmission . the phr must be available in the frame buffer before this time elapses. further more t he spi data rate must be higher than the phy data rate selected by register bits oqpsk_data_rate ( register 0x 0c, trx_ctrl_2) to ensure that no frame buffer unde r run occurs, indicated by irq_6 ( trx_ur ) , refer to section 11.3 . figure 10 - 3 . time optimized frame transmit procedure . a t 8 6 r f 2 3 3 m i c r o c o n t r o l l e r w r i t e f r a m e d a t a ( f r a m e b u f f e r a c c e s s ) w r i t e t r x _ c m d = t x _ s t a r t , o r a s s e r t p i n 1 1 ( s l p _ t r ) i r q _ 3 ( t r x _ e n d ) i s s u e d r e a d i r q _ s t a t u s r e g i s t e r , p i n 2 4 ( i r q ) d e a s s e r t e d i r q _ 3 ( t r x _ e n d ) i s s u e d w r i t e f r a m e d a t a ( f r a m e b u f f e r a c c e s s ) w r i t e t r x _ c m d = t x _ s t a r t , o r a s s e r t p i n 1 1 ( s l p _ t r ) a t 8 6 r f 2 3 3 m i c r o c o n t r o l l e r r e a d i r q _ s t a t u s r e g i s t e r , p i n 2 4 ( i r q ) d e a s s e r t e d
130 8351b C C AT86RF233 11 AT86RF233 extended feature set 11.1 security module (aes) the security module (aes) is characterized by : ? hardware accelerated encryption and decryption ? compatible with aes - 128 standard (128 - bit key and data block size) ? ecb (encryption/decryption) mode and cbc (encryption) mode support ? stand - alone operation, independent of other blocks 11.1.1 overview the security module is based on an aes - 128 core according to fips197 standard, refer to [ 6 ] . the security module work s independent of other building blocks of the atmel AT86RF233 , encryption and decryption can be performed in parallel to a frame transmission or reception . controlling the security block is implemented as an sram access to address space 0x82 to 0x94 . a fast sram access mode allows simultaneously writing new data and reading data from previously processed data within the same spi transfer. this acce ss procedure is used to reduce the turnaround time for ecb and cbc mode s , see section 11.1.5 . in addition , the security module contains another 128 - bit register to store the initial key used for security operations. this initial key is not m odified by the security module. 11.1.2 security module preparation the use of the security module requires a configuration of t he security engine before starting a security operation. the following steps are required: table 11 - 1 . aes engine configuration steps . step description description section 1 key setup write encryption or decryption key to sram 11.1.3 2 aes mode select aes mode: ecb or cbc select encryption or decryption 11.1.4.1 11.1.4.2 3 write data write plaintext or cipher text to sram 11.1.5 4 start operation start aes operation 5 read data read cipher text or plaintext from sram 11.1.5 before starting any security operation , a key must be written to the security engine, refer to section 11.1.3 . t he key set up requires the configuration of the aes engine key mode using register bits aes_mode (sram address 0x83, aes_ctrl ). the following step selects the aes mode, either electronic co de book (ecb) or cipher block chaining (cbc). these modes are explained in more detail in section 11.1.4 . further , encryption or decryption must be selected with register bit aes_dir ( sram address 0x83, aes_ctrl ). after this, the 128 - bit plain text or cipher text data has to be provided to the aes hardware engine. the data uses the sram address range 0x84 C 0x93.
131 8351b C C AT86RF233 an encryption or decryption is initiated with register bit aes_request = 1 (sram address 0x83, that is aes_ctrl, or the mirrored version sram address 0x94, that is aes_ctrl_mirror). the aes module control registers are only accessible using sram read and w rite accesses on address space 0x82 to 0x94. configuring the aes mode, providing the data, and starting a decryption or encryption operation can be combined in a single sram access . notes: 1. no additional register access is required to operate the security block. 2. access to the security block is not possible while the radio transceiver is in sleep, deep_sleep , or reset state . 3. all configurations of the security module, the sram content, and keys are reset d uring deep_sleep or reset state . 4. a read or write access to register 0x83 (aes_ctrl) during aes operation terminates the current processing. 11.1.3 security key setup the setup of the key is prepared by setting r egister bits aes_mode = 1 ( sram address 0x83, aes_ctrl ) . afterwards the 128 - bit key must be written to sram address es 0x84 through 0x93 (registers aes_key ). it is recommended to combine the setting of control register 0x 83 ( aes_ctrl ) and the 128 - bit key transfer using only one sram access starting from address 0x83 . the address space for the 128 - bit key and 128 - bit data is identical from programming point of view. however, both use different pages which are selected by register bit aes_mode before storing the data. a read access to register s aes_key (0x84 C 0x93) returns the last round key of the preceding s ecurity operation. after an ecb encryption operation, this is the key that is required for the corresponding ecb decryption operation. however, t he initial aes key , written to the securit y module in advance of an aes run, see step one in table 11 - 1 , is not modified during an aes operation. this initial key is used for the next aes run even it cannot be read from aes_key . note: 1. ecb decryption is not required for ieee 802.15.4 or zigbee s ecurity processing. the atmel AT86RF233 provides this functionality as an additional feature. 11.1.4 security operation modes 11.1.4.1 electronic code book (ecb) ecb is the basic operati ng mode of the security module . after setting up the initial aes key, register bits aes_mode = 0 ( sram address 0x83, aes_ctrl ) sets up ecb mode. register bit aes_dir ( sram address 0x83, aes_ctrl ) selects the direction, either encryption or decryption. the data to be processed has to be written to sram address es 0x8 4 through 0x93 (registers aes_state ). an example for a programming sequence is shown in figure 11 - 1 . this example assumes a suitable key has been loaded before. a security operation can be started within one sram access by appending the start command aes_request = 1 ( register 0x 94, ae s_ctrl _mirror) to the spi sequence. register aes_ctrl _mirror is a mirrored version of register 0x 83 ( aes_ctrl ).
132 8351b C C AT86RF233 figure 11 - 1 . ecb programming spi sequence C encryption . summarizing , the following steps are required to perform a security operation using only one atmel AT86RF233 spi access: 1. configure spi access a) sram write, refer to section 6.3.3 b) start address 0x83 2. configure aes operation address 0x83: select ecb mode, direction 3. write 128 - bit data block addresses 0x84 C 0x93: either plain or ciphertext 4. start aes operation address 0x94: start aes operation, ecb mode this sequence is recommended because the security operation is configured and started within one spi transaction . t he ecb encryption operation is illustrated in figure 11 - 2 . figure 11 - 3 shows the ecb decryption mode , which is supported in a similar way. figure 11 - 2 . ecb mode C encryption . figure 11 - 3 . ecb mode C decryption . 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 byte 1 ( address ) byte 0 ( cmd .) byte 18 . 1 0 0 0 0 0 0 0 data _ 15 [ 7 : 0 ] byte 19 ( aes cmd ) byte 2 ( aes cmd ) data _ 0 [ 7 : 0 ] byte 3 ecb , encryption 0 x 83 sram write aes start block cipher encryption encryption key plaintext ciphertext block cipher encryption encryption key plaintext ciphertext block cipher decryption decryption key plaintext ciphertext block cipher decryption decryption key plaintext ciphertext
133 8351b C C AT86RF233 when decrypting, due to the nature of aes algorithm, the initial key to be used is n ot the same as the one used for encryption, but rather the last round key instead. this last round key is the content of the key address space store d after running one full encryption cycle , and must be saved for decryption. if the decryption key has not b een saved, it has to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching the resulting round key from the key memory , and writing it back into the key memory as the decryption key. ecb decryption is not used by either ieee 802.15.4 or zigbee frame security. both of these standard s do not directly encrypt the payload, but rather a nonce instead, and protect the payload by applying an xor operation between the resulting (aes - ) cipher text and the original payload. as the nonce is the same for encryption and decryption only ecb encryption is required. decryption is performed by xoring the received cipher text with its own encryption result respectively, which results in the orig inal plaintext payload upon success. 11.1.4.2 cipher block chaining (cbc) in cbc mode , the result of a previous aes operation is xored with the new incoming vector, forming the new plaintext to encrypt, see figure 11 - 4 . this mode is used for the computation of a cryptographic checksum (message integrity code, mic ). figure 11 - 4 . cbc mode C encryption . after preparing the aes key and defining the aes operation direction using atmel AT86RF233 sram register bit aes_dir , the data has to be provided to the aes engine and th e cbc operation can be started. t he first cbc run has to be configured as ecb to process the initial data (plaintext xored with an initialization vector provided by the microcontroller ) . all succeeding aes runs are to be configured as cbc by setting register bits aes_mode = 2 ( register 0x 83, aes_ctrl ). r egister bit aes_dir ( register 0x 83, aes_ctrl ) must be set to aes_dir = 0 to enable aes encryption. the data to be processed has to be transferred to the sram starting with address 0x84 to 0x93 (register aes_state ). set ting register bit aes_request = 1 ( register 0x 94, aes_ctrl _ mirror ) as described in section 11.1.4 start s the first encryption with in one sram access . this cause s the next 128 bits of plaintext data to be xored with the previous cipher text data , see figure 11 - 4 . according to ieee 802.15.4 the input for the very first cbc operation has to be prepared by a xoring a plaintext with an initialization vector (iv). the value of the block cipher encryption encryption key ciphertext block cipher encryption plaintext ciphertext plaintext initialization vector ( iv ) encryption key ecb mode cbc mode
134 8351b C C AT86RF233 initialization vector is zero . however, for non - compliant usage any other initialization v ector can be used. this operation has to be prepared by the microcontroller. note: 1. the ieee 802.15.4 - 2006 standard mic algorithm requires cbc mode encryption only, as it implements a one - way hash function. 11.1.5 data transfer C fast sram access the ecb and cbc modules including the aes core are clocked with 16 mhz . one aes operation takes t aes = 23.4 s to execute , refer to table 7 - 2 . that means that the processing of the data is usually faster than the transfer of the data via the spi interface. to reduce the overall processing time the atmel AT86RF233 provides a fast sram access for the address space 0x8 2 to 0x94 . figure 11 - 5 . packet structure C fast sram access mode . note: 1. byte 19 is the mirrored version of register aes_ctrl on sram address 0x94, see register description aes_ctrl_mirror for details. in contrast to a standard sram access, refer to section 6.3.3 , the fast sram access allows writing and reading of data simultaneously during one spi access for con secutive aes operations ( aes run ) . for each byte p0 transferred to pin 22 (mosi) for example in D aes access #1 , see figure 11 - 5 (lower part) , the previous content of the respective aes register c0 is clocked out at pin 20 (miso) with an offset of one byte . in th e example shown in figure 11 - 5 the initial plaintext p0 C p15 is written to the sram within D aes access #0 . the last command on address 0x94 ( aes_ctrl _mirror) starts the aes operation (D aes run #0 ) . in the next D aes access #1 new plaintext data p0 C p15 is written to the sram for the second aes run, in parallel the ciphertext c0 C c15 from the first aes run is clocked out at pin miso. to read the ciphertext from the last D aes run #(n) one dummy D aes access # ( n +1) is needed. note: 2. the sram write access always overwrites the previous processing result. sram write mosi phy _ status miso byte 0 ( cmd ) address 0 x 83 xx < aes _ ctrl > xx byte 1 ( addr .) byte 2 ( cfg ) p 0 [ 7 : 0 ] xx byte 3 byte 4 byte 18 < aes _ ctrl > ( 1 ) byte 19 ( start ) 0 x 83 0 x 85 0 x 84 0 x 93 0 x 94 address mosi miso aes access # 0 address p 0 p 15 ... cmd add cfg start xx xx ... stat xx xx xx 0 x 83 0 x 94 ... aes access # 1 p 0 p 15 ... cmd add cfg start xx c 14 ... stat xx xx c 15 0 x 83 0 x 94 ... aes access # n + 1 xx xx ... cmd add cfg start xx c 14 ... stat xx xx c 15 0 x 83 0 x 94 ... p 1 p 14 xx xx p 1 p 14 c 0 c 13 xx xx c 0 c 13 ... ... c 0 [ 7 : 0 ] p 1 [ 7 : 0 ] c 14 [ 7 : 0 ] c 15 [ 7 : 0 ] p 15 [ 7 : 0 ] aes run # 0 aes run # n . . .
135 8351b C C AT86RF233 the fast sram access automatically applies to all write operations to sram addresses 0x8 2 to 0x94 . 11.1.6 start of security operation and status a security operation is started within one atmel AT86RF233 sram access by appending the start command aes_request = 1 ( register 0x 94, aes_ctrl _mirror) to the spi sequence. register aes_ctrl _mirror is a mirrored version of register 0x 83 ( aes_ctrl ). the status of the security processing is indicated by register 0x 82 ( aes_st atus ). after t aes = 24 s (max.) aes processing time register bit aes_done changes to one ( register 0x 82, aes_st atus ) i ndicating that the security operation has finished . 11.1.7 sram register summary the following registers are required to control the security module: table 11 - 2 . sram security module address space overview . sram - addr. register name description 0x80 C 0x81 reserved 0x82 aes_status aes status 0x83 aes_ctrl security module control, aes mode 0x84 C 0x93 aes_key aes_state depends on aes_mode setting: aes_mode = 1: - contains aes_key (key) aes_mode = 0 | 2: - contains aes_state (128 bit data block) 0x94 aes_ctrl_mirror mirror of register 0x83 (aes_ctrl) 0x95 C 0xff reserved these registers are only accessible using sram write and read accesses , for details refer to section 6.3.3 . note: 1. the aes registers are reset when entering the deep_sleep state . 11.1.8 register description register 0x82 (aes_status): the read - only register aes_status signals the status of the security module and operation. figure 11 - 6 . register aes_status. bit 7 6 5 4 0x82 aes_er reserved aes_status read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x82 reserved aes_done aes_status read/write r r r r reset value 0 0 0 0
136 8351b C C AT86RF233 ? bit 7 - aes_er this sram register bit indicates an error of the aes module. an error may occur for instance after an access to sram register 0x83 (aes_ctrl) while an aes operation is running or after reading less than 128 - bits from sram register space 0x84 C 0x93 (aes_st ate). table 11 - 3 . aes_er. register bits value description aes_er 0 no error of the aes module 1 aes module error ? bit 0 - aes_done the bit aes_done signals the status of aes operation. table 11 - 4 . aes_done. register bits value description aes_done 0 aes operation has not been completed 1 aes operation has been completed register 0x83 (aes_ctrl): the aes_ctrl register controls the operation of the security module. figure 11 - 7 . register aes_ctrl. bit 7 6 5 4 0x83 aes_request aes_mode aes_ctrl read/write w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x83 aes_dir reserved aes_ctrl read/write r/w r r r reset value 0 0 0 0 notes: 1. do not access this register during aes operation to read the aes core status. a read or write access during aes operation stops the actual processing. 2. to read the aes status use register bit aes_done (register 0x82, aes_status). ? bit 7 - aes_request a write access with aes_request = 1 initiates the aes operation. table 11 - 5 . aes_request. register bits value description aes_request 0 security module, aes core idle 1 a write access starts the aes operation
137 8351b C C AT86RF233 ? bit 6:4 - aes_mode this register bit sets the aes operation mode. table 11 - 6 . aes_mode. register bits value description aes_mode 0 ecb mode 1 key mode 2 cbc mode all other values are reserved ? bit 3 - aes_dir the register bit aes_dir sets the aes operation direction, either encryption or decryption. table 11 - 7 . aes_dir. register bits value description aes_dir 0 aes encryption (ecb, cbc) 1 aes decryption (ecb) register 0x 94 ( aes_ctrl _ mirror ): register 0x 94 is a mirrored version of register 0x 83 ( aes_ctrl ), for details refer to register 0x 83 ( aes_ctrl ) . this register could be used to start a security operation with in a single sram access by appending it to the data stream and set ting register bit aes_request = 1.
138 8351b C C AT86RF233 11.2 random number generator 11.2.1 overview the atmel AT86RF233 incorporates a two bit truly random number generator by observation of noise. this random number can be used to: ? g enerate random seeds for csma - ca algorithm see section 7.2 ? g enerate random values for aes key generation see section 11.1 the random number is updated every t rnd = 1 s in basic op eration mode receive states. the values are stored in register bits rnd_value ( register 0x 06, phy_rssi). 11.2.2 register description register 0x06 (phy_rssi): the phy_rssi register is a multi - purpose register that indicates fcs validity, to provide random numbers , and a rssi value. figure 11 - 8 . register phy_rssi. bit 7 6 5 4 0x06 rx_crc_valid rnd_value rssi phy_rssi read/write r r r r reset value 0 1 1 0 bit 3 2 1 0 0x06 rssi phy_rssi read/write r r r r reset value 0 0 0 0 ? bit 6:5 - rnd_value the 2 - bit random value can be retrieved by reading register bits rnd_value. table 11 - 8 . rnd_value. register bits value description rnd_value 3 deliver two bit noise value within receive state. valid values are [3, 2, , 0]. note: 1. the radio transceiver shall be in basic operating mode receive state.
139 8351b C C AT86RF233 11.3 high data rate mode s the main features are: ? high d ata r ate transmission up to 2 000k b/s . ? support of basic and extended operating mode ? support of other features of the extended feature set 11.3.1 overview the atmel AT86RF233 also support s alternative data rates , higher than 250 kb/s for applications beyond ie ee 802.15.4 compliant networks . the selection of a data rate does not affect the rem aining functionality. thus it is possible to run all features and operating modes of the radio transceiver in various combinations . the data rate can be selected by writing to register bits oqpsk_data_rate ( register 0x 0c, trx_ctrl_2). the high data rate modes occupy the same rf channel bandwidth as the ieee 802.15.4 C 2.4 ghz 250 kb/s standard mode. due to the decreased spreading factor , t he sensitivity of the receiver is reduced accordingly . table 11 - 9 shows typical values of the sensitivity for different data rates . table 11 - 9 . high data rate sensitivity for awgn channel . high data rate sensitivity comment 250 kb/s - 101 dbm per 1%, psdu length of 20 octets 500 kb/s - 96 dbm per 1%, psdu length of 20 octets 1000 kb/s - 94 dbm per 1%, psdu length of 20 octets 2000 kb/s - 88 dbm per 1%, psdu length of 20 octets by default there is no header based signaling of the data rate with in a transmitted frame. thus nodes using a data rate other than the default ieee 802.15.4 data rate of 250 kb/s are to be configured in advance and consistently . alternatively , the configurable start of frame delimiter (sfd) could be used as an indicator of the phy data rate, see section 11.9 .
140 8351b C C AT86RF233 11.3.2 high data rate packet structure in order to allow appropriate frame synchronization, atmel AT86RF233 higher data rate modulation is restricted to the payload octets only. the shr and the phr field are transmitted with the ieee 802.15.4 compliant data rate of 250 kb/s , refer to section 8.1.1 . a comparison of the general packet structure for different data rate s with a n example psdu length of 80 octets is shown in figure 11 - 9 . figure 11 - 9 . high data rate frame structure . due to the overhead caused by the shr, phr as well as the fcs , the effective data rate is lower than the selected data rate. this is also affected by t he length of the psdu. a graphical representation of the effective psdu data rate is shown in figure 11 - 10 . figure 11 - 10 . effective data r ate Db for high data rate mode . the effective throughput is further affected by the mac overhead, the acknowledgment scheme as well as the microcontroller processing capability. consequently, high data 250 kb / s 0 time [ s ] 192 s f d p h r 832 1472 2752 500 kb / s s f d p h r 1000 kb / s s f d p h r 2000 kb / s s f d p h r 512 f c s f c s psdu : 80 octets psdu : 80 octets psdu : 80 octets psdu : 80 octets 0 200 400 600 800 1000 1200 1400 1600 0 20 40 60 80 100 120 psdu length in octets b [kb/s] 2000 1000 500 250 2000 kb/s 1000 kb/s 500 kb/s 250 kb/s
141 8351b C C AT86RF233 rate transmission and reception is useful for large psdu lengths due to the higher effective data rate, or to reduce the power consumption of the system. when using high data rate modes the active on - air time is significantly reduced. 11.3.3 high data rate frame buffer access the atmel AT86RF233 frame buffer access to read or write frames for high data rate transmission is similar to the procedure described in section 6.3.2 . howe ver, during frame buffer read access the nex t byte transferred after the psdu data is the lqi value. this value is invalid for the high data rates. figure 11 - 11 illustrates the packet structure of a high data rate frame buffer read access. figure 11 - 11 . packet structure - high dat a rate frame buffer read access . the structure of rx_status is described in table 6 - 3 . 11.3.4 high data rate energy detection according to ieee 802.15.4 t he ed measurement duration is eight symbol periods. for frames operated at higher data rate s the automated ed measurement duration is reduced to 32 s to take the reduced frame length into account , refer to section 8.4 . during frame buffer read access the ed value is appended to the psdu data, refer to section 11.3.3 . 11.3.5 high data ra te mode options receiver sensitivity control the different data rates between ppdu header (shr and phr) and phy payload (psdu) cause a different sensitivity between header and payload. this can be adjusted by defining sensitivity threshold levels of the receiver. with a sensitivity threshold level rx_pdt_level > 0 (register 0x15, rx_syn ), the receiver does not receive frames with an rssi leve l below that threshold. under th ese operati n g conditions the receiver current consumption is reduced to 11.3 ma , refer to section 12.8 parameter i rx_on_l0 . enabling receiver sensitivity control with at least rx_pdt_level = 1 is recommended for the 2 000k b/s rate with a psdu sensitivity of - 88 dbm . in the case of receiving with the default setting of rx_pdt_level , a high data rate frame may be detected even if the psdu sensitivity is above the received signal strength. in this case the frame is rejected. a description of the setting s to control th e sensitivity threshold rx_pdt_level (register 0x15, rx_syn) can be found in section 9.1.4 . 0 r e s e r v e d [ 4 : 0 ] 0 m o s i p h y _ s t a t u s m i s o b y t e 1 ( c o m m a n d b y t e ) 1 x x p h r [ 7 : 0 ] b y t e 2 ( d a t a b y t e ) x x p s d u [ 7 : 0 ] b y t e 3 ( d a t a b y t e ) x x e d [ 7 : 0 ] b y t e n - 1 ( d a t a b y t e ) x x r x _ s t a t u s [ 7 : 0 ] b y t e n ( d a t a b y t e )
142 8351b C C AT86RF233 scrambler for data rate 2000 kb/s , additional chip scrambling is applied per default, in order to mitigate data dependent spectral properties. scrambling can be disabled if atmel at8 6rf233 register bit oqpsk_scram_en (register 0x0c, trx_ctrl_2) is set to zero . carrier sense for clear channel assessment, ieee 802.15.4 - 2006 specifies several modes which may either apply energy above threshold or carrier sense (cs) or a combination of both. in high data rate modes only Denerg y above threshold is supported, since the modulation spreading is not compliant to ieee 802.15.4 - 2006. link quality indicator (lqi) for the high data rate modes, the link quality indicator does not contain useful information and should be discarded. reduced acknowledgment t iming on higher data rates the ieee 802.15.4 compliant acknowledgment frame response time of 192 s significantly reduces the effective data rate of the network. to minimize this influence in extended operating mode rx_aack, refer to section 7.2.3 , the acknowledgment frame response time can be reduced to 32 s . figure 11 - 12 illustrates an example for a reception and acknowledgement of a frame with a data rate of 2000 kb/s and a psdu length of 80 symbols. the psdu length of the acknowledgment frame is five octets according to ieee 802.15.4. figure 11 - 12 . high data rate aack timing . if register bit aack_ack_time ( register 0x 17, xah_ctrl_1) is set the acknowledgment time is reduced from 192 s to 32 s . 0 time [ s ] 192 512 aack _ ack _ time = 0 psdu : 80 octets s f d p h r s f d p h r 704 916 32 s psdu : 80 octets s f d p h r s f d p h r 192 s 544 aack _ ack _ time = 1 ack ack
143 8351b C C AT86RF233 11.3.6 register description register 0x0c (trx_ctrl_2): the trx_ctrl_2 register is a multi - purpose control register to control various settings of the radio transceiver. figure 11 - 13 . register trx_ctrl_2. bit 7 6 5 4 0x0c rx_safe_mode reserved oqpsk_scram_ en reserved trx_ctrl_2 read/write r/w r r/w r reset value 0 0 1 0 bit 3 2 1 0 0x0c reserved oqpsk_data_rate trx_ctrl_2 read/write r r/w r/w r/w reset value 0 0 0 0 ? bit 5 - oqpsk_scram_en if register bit oqpsk_scram_en is enabled, an additional chip scrambling is applied for 2000kb/s data rate. table 11 - 10 . oqpsk_scram_en. register bits value description oqpsk_scram_en 0 scrambler is disabled 1 scrambler is enabled ? bit 2:0 - oqpsk_data_rate a write access to these register bits set the oqpsk psdu data rate used by the radio transceiver. the reset value o - qpsk_data_rate = 0 is the psdu data rate according to ieee 802.15.4. ta ble 11 - 11 . oqpsk_data_rate. register bits value description oqpsk_data_rate 0 (1) 250kb/s 1 500kb/s 2 1000kb/s 3 2000kb/s all other values are reserved note: 1. ieee 802.15.4 compliant.
144 8351b C C AT86RF233 register 0x15 (rx_syn): the register rx_syn controls the blocking of receiver path and the sensitivity threshold of the receiver. figure 11 - 14 . register rx_syn. bit 7 6 5 4 0x15 rx_pdt_dis reserved rx_syn read/write r/w r r r reset value 0 0 0 0 bit 3 2 1 0 0x15 rx_pdt_level rx_syn read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 3:0 - rx_pdt_level the register bits rx_pdt_level desensitize the receiver in steps of 3db. table 11 - 12 . rx_pdt_level. register bits value description rx_pdt_level 0x00 maximum rx sensitivity 0x0f rx input level > rssi_base_val + 3[db] x 14 register 0x17 (xah_ctrl_1): the xah_ctrl_1 register is a multi - purpose controls register for extended operating mode. figure 11 - 15 . register xah_ctrl_1. bit 7 6 5 4 0x17 aret_tx_ts_en reserved aack_fltr_res_ ft aack_upld_res_ ft xah_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x17 reserved aack_ack_time aack_prom_ mode aack_spc_en xah_ctrl_1 read/write r r/w r/w r/w reset value 0 0 0 0 ? bit 2 - aack_ack_time the register bit aack_ack_time controls the acknowledgment frame response time within rx_aack mode. table 11 - 13 . aack_ack_time. register bits value description aack_ack_time 0 acknowledg ment time is 12 symbol periods (aturnaroundtime) 1 acknowledgment time is two symbol periods
145 8351b C C AT86RF233 according to ieee 802.15.4 - 2006 , section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aturnaroundtime) after the reception of the last symbol of a data or mac command frame. this is achieved with the reset value of the register bit aack_ack_tim e. alternatively, if aack_ack_time = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or mac command frame. this may be applied to proprietary networks or networks using the high data rate modes to increase battery lifetime and to improve the overall data throughput .
146 8351b C C AT86RF233 11.4 antenna diversity the a ntenna d iversity implementation is characterized by : ? improves signal path robustness between nodes ? atmel AT86RF233 self - contained antenna diversity algorithm ? direct register based antenna selection 11.4.1 overview due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality , even for small changes of the antenna location . these fading effects can result in an increased error floor or loss of the connection between devices. to improve the reliability of a n rf connection between network nodes a ntenna d iversity can be applied to reduce effects of multipath propagation and fading. antenna d iversity uses two antennas to select the most reliable rf signal path. to ensur e highly independent receive signals on both antennas, the antennas should be carefully separated from each other. if a valid ieee 802.15.4 fram e is detected on one antenna , this antenna is selected for reception . otherwise the search is continued on the other antenna and vice versa. antenna d iversity can be used in basic and extended operating modes and can also be combined with other features an d operating modes like high data rate mode and rx/tx indication. 11.4.2 antenna diversity application example a block diagram for an application using an antenna switch is shown in figure 11 - 16 . figure 11 - 16 . antenna diversity C block diagram . generally, if the antenna diversity used t he control of an antenna diversity switch must be enabled by register bit ant_ext_sw_en ( register 0x 0d, ant_div). t he internal connection to digital ground of the control pins pin 9 (dig1) and pin 10 (dig2) is disabled (refer to section 1.3 ) , and they feed the antenna switch signal and its inverse to the differential inputs of the rf switch (sw1) . 6 5 4 3 2 1 9 1 0 a t 8 6 r f 2 3 3 d i g 3 d i g 4 a v s s r f p r f n a v s s d i g 1 d i g 2 b a l u n a n t 0 a n t 1 r f - s w i t c h b 1 s w 1 . . .
147 8351b C C AT86RF233 if the atmel AT86RF233 is not in a receive or transmit state , it is recommended to disable register bit ant_ext_sw_en to reduce the power consumption or avoid leakage current of an external rf switch, especially during sleep or deep_sleep state. if register bit ant_ext _sw_en = 0, output pins dig1/dig2 are pulled - down to digital ground. user defined antenna selection a microcontroller defined selection of a certain antenna can be done by disabling the automated antenna diversity algorithm (ant_div_en = 0) and selecting one antenna using register bits ant_ctrl = 1 / 2. the antenna defined by register bits ant_ctrl (register 0x0d, ant_div) is used for transmission and reception. autonomous antenna selection t he autonomous antenna diversity algorithm is enabled with regist er bit s ant_div_en = 1 and ant_ctrl = 0 / 3 (register 0x0d, ant_div) . it allows the use of antenna diversity even if the microcontroller does currently not control the radio transceiver, for instance in extended operating mode. upon reception of a frame , the AT86RF233 selects one antenna. the selected antenna is then indicated by register bit ant_sel (register 0x0d, ant_div). if required, i t is recommended to read register bit ant_sel after irq_2 ( rx_start ) . after the frame reception is completed, the antenna selection continues searching for new frames on both antennas. however, the register bit ant_ sel maintains its previous value (from the last received frame) until a new ieee 802.15.4 frame has been detected , and the selection algorithm locked into one antenna again. at this time the register bit ant_sel is updated again. if a device is in rx_aack mode , receiving a frame containing an ack request, the ack frame is transmitted using the same antenna as used during receive. if a device performs a transaction in tx_aret mode, it starts to listen for an ack on the transmit antenna. if no ack was received, the next transmission attempt is done on the other transmit antenna. this will be repeated with each retry. 11.4.3 antenna diversi ty sensitivity control due to a different receive algorithm used by the antenna diversity algorithm, the correlator threshold of the receiver has to be adjusted . it is recommended to set register bits pdt_thres ( register 0x 0a, rx_ctrl) to three .
148 8351b C C AT86RF233 11.4.4 register description register 0x0a (rx_ctrl): the rx_ctrl register controls the sensitivity of the antenna diversity mode and indicates the receiver synchronization behavior. figure 11 - 17 . register rx_ctrl. bit 7 6 5 4 0x0a reserved rx_ctrl read/write r r r/w r/w reset value 0 0 1 1 bit 3 2 1 0 0x0a pdt_thres rx_ctrl read/write r/w r/w r/w r/w reset value 0 1 1 1 ? bit 3:0 - pdt_thres the register bits pdt_thres control the sensitivity of the receiver correlation unit. table 11 - 14 . pdt_thres. register bits value description pdt_thres 0x3 (1) recommended correlator threshold for antenna diversity operation 0x7 to be used if antenna diversity algorithm is disabled all other values are reserved note: 1. if the antenna diversity algorithm is enabled (ant_div_en = 1), the value shall be set to pdt_thres = 3, otherwise it shall be set back to the reset value. this is not automatically done by the hardware. register 0x0d (ant_div): the ant_div register co ntrols antenna diversity. figure 11 - 18 . register ant_div. bit 7 6 5 4 0x0d ant_sel reserved ant_div read/write r r r r reset value 0 0 0 0 bit 3 2 1 0 0x0d ant_div_en ant_ext_sw_en ant_ctrl ant_div read/write r/w r/w r/w r/w reset value 0 0 0 0
149 8351b C C AT86RF233 ? bit 7 - ant_sel signals selected antenna, related to the last received frame. table 11 - 15 . ant_sel. register bits value description ant_sel 0 antenna 0 1 antenna 1 note: 1. if the autonomous antenna diversity algorithm is enabled, the register bit ant_sel maintains its previous value (from the last received frame) until a new shr has been found. this register bit signals the currently selected antenna path. the selection may be based either on the last antenna diversity cycle (ant_div_en = 1) or on the content of register bits ant_ctrl, for details refer to section 11.4.2 . ? bit 3 - ant_div_en the register bit ant_div_en activates the autonomous antenna diversity algorithm. table 11 - 16 . ant_div_en. register bits value description ant_div_en 0 antenna diversity algorithm is disabled 1 antenna diversity algorithm is enabled note: 1. if ant_div_en = 1 register bit ant_ext_sw_en shall be set to one, too. this is not automatically done by the hardware. if register bit ant_div_en is set the antenna diversity algorithm is enabled. on reception of a frame the algorithm selects an antenna autonomously during shr search. this selection is kept until: ? a new shr search starts ? leaving receive states ? r egister bits ant_ctrl are manually programmed ? bit 2 - ant_ext_sw_en the register bit ant_ext_sw_en controls the external antenna switch. table 11 - 17 . ant_ext_sw_en. register bits value description ant_ext_sw_en 0 antenna diversity rf switch control is disabled 1 antenna diversity rf switch control is enabled if enabled, pin 9 (dig1) and pin 10 (dig2) become output pins and provide a differential control signal for an antenna diversity switch. the selection of a specific antenna is done either by the automated antenna diversity algorithm (ant_div_en = 1), or ac cording to register bits ant_ctrl if antenna diversity algorithm is disabled. if the atmel AT86RF233 is not in r eceive or transmit state, it is recommended to disable register bit ant_ext_sw_en to reduce the power consumption or avoid leakage current of an external rf switch, especially during sleep or deep_sleep state. if register bit ant_ext_sw_en = 0, output pins dig1 and dig2 are pulled - down to digital ground.
150 8351b C C AT86RF233 pin 10 (dig2) is overloaded with rx and tx frame ti me stamping, see section 11.6 , if irq_2_ext_en is set. ? bit 1:0 - ant_ctrl these register bits provide a static control of an antenna diversity switch. table 11 - 18 . ant_ctrl. register bits value description ant_ctrl 0 mandatory setting for applications not using antenna diversity and if autonomous antenna selection is enabled 1 antenna 0 dig1 = l dig2 = h 2 antenna 1 dig1 = h dig2 = l 3 same behavior as value zero
151 8351b C C AT86RF233 11.5 rx /tx indicator the main features are: ? rx/tx indicator to control an external rf f ront - e nd ? microcontroller i ndependent rf front - end control ? providing tx timing information 11.5.1 overview while ieee 802.15.4 is targeting low cost a nd low power applications, solutions supporting higher transmit output power are occasionally desirable. to simplify the control of an external rf front - end, a differential control pin pair indicate s the atmel AT86RF233 operating mode. the control of an external rf front - end is done via digital control pins dig3/dig4 , enabled with register bit pa_ext_en (register 0x04, trx_ctrl_1) set . if the AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit pa_ext_en (register 0x04, trx_ctrl_1) to reduce the power consumption or avoid leakage current of external rf switches and other building blocks, especially during sleep or de ep_sleep state. if register bit pa_ext_en = 0, output pins dig3/dig4 are pulled - down to analog ground. 11.5.2 external rf - front end control the timing of an external rf front - end relative to the radio transceiver sequencing is shown in figure 11 - 19 and figure 11 - 20 , focussing on the tx indication. a posedge of pin slp_tr initiates a transmission, refer to section 9.2 . the radio transceiver control switches the differential pin pair dig3/4 6 s after tx request recognition to tx operating mode indication. after finishing the transmission, as shown in figure 11 - 20 , pin pair dig3/4 is switched back to rx operating mode indication 3 s after disabling the AT86RF233 internal pa. figure 11 - 19 . tx power up ramping control for rf front - ends for maximum tx p ower . 0 6 8 1 0 t r x _ s t a t e s l p _ t r p l l _ o n 2 1 2 1 4 1 6 1 8 l e n g t h [ s ] p a b u f f e r 4 p a d i g 3 d i g 4 m o d u l a t i o n 1 1 0 0 0 0 0 0 1 b u s y _ t x 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1
152 8351b C C AT86RF233 figure 11 - 20 . tx power down ramping for maximum tx power . 11.5.3 register description register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver. figure 11 - 21 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 7 C pa_ext_en th e register bit pa_ext_en enables pin 1 (dig3) and pin 2 (dig4) to indicate the transmit state of the radio transceiver. table 11 - 19 . rf front - end control pins . pa_ext_en state pin value description 0 n/a dig3 l external rf front - end control disabled dig4 l 1 (1) tx_busy dig3 h external rf front - end control enabled dig4 l other dig3 l dig4 h note: 1. it is recommended to set pa_ext_en = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external rf switches or other building blocks , especially during sleep or deep_sleep state. 0 6 t r x _ s t a t e b u s y _ t x 2 l e n g t h [ s ] p a b u f f e r 4 p a d i g 3 d i g 4 m o d u l a t i o n 1 1 0 0 0 1 p l l _ o n 0 1 1 0 1 0 1 0 0 1
153 8351b C C AT86RF233 11.6 rx and tx frame time stamping (tx_aret) 11.6.1 overview an exact timing of received and transmitted frame s is signaled by atmel AT86RF233 pin 10 (dig2). a valid phr rece ption or start of frame transmission is indicated by a dig2 p osedge . the pin remains high dur ing frame reception or transmission . tx frame time stamping is limited to tx_aret, whereas the rx frame time stamping is available for all receive modes. exemplary, figure 11 - 22 illustrates a frame reception example . figure 11 - 22 . timing of rx_start and dig2 for rx frame time stamping . note: 1. timing figures t irq refer to s ection 12.4 . if p in 10 (dig2) is not used for rx and /or tx frame time stamping , or antenna d iversity, it is pulled - down to digital ground . 11.6.2 register description register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver. figure 11 - 23 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 128 160 192 0 192 + m * 32 time [ s ] r x f r a m e o n a i r irq _ 2 ( rx _ start ) t irq rx _ on rx _ on irq trx _ state interrupt latency preamble sfd phr psdu ( 250 kb / s ) 4 1 1 m < 128 number of octets frame content trx _ end t irq busy _ rx dig 2 ( rx frame time stamp )
154 8351b C C AT86RF233 ? bit 6 - irq_2_ext_en the register bit irq_2_ext_en controls external signaling for time stamping via pin 10 (dig2). table 11 - 20 . irq_2_ext_en. register bits value description irq_2_ext_en 0 time stamping over pin 10 (dig2) is disabled 1 (1) time stamping over pin 10 (dig2) is enabled notes: 1. the pin 10 (dig2) is also active if the corresponding interrupt event irq_2 (rx_start) mask bit in register 0x0e (irq_mask) is set to zero. 2. the pin remains at high level until the end of the frame receive or transmit procedure. register 0x17 (xah_ctrl_1): the xah_ctrl_1 register is a multi - purpose controls register for extended operating mode. figure 11 - 24 . register xah_ctrl_1. bit 7 6 5 4 0x17 aret_tx_ts_en reserved aack_fltr_res_ ft aack_upld_res_ ft xah_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x17 reserved aack_ack_time aack_prom_ mode aack_spc_en xah_ctrl_1 read/write r r/w r/w r/w reset value 0 0 0 0 ? bit 7 - aret_tx_ts_en if register bit aret_tx_ts_en = 1, then any frame transmission within tx_aret mode is signaled via pin 10 (dig2). table 11 - 21 . aret_tx_ts_en. register bits value description aret_tx_ts_en 0 tx_aret time stamping via pin 10 (dig2) is disabled 1 (1) tx_aret time stamping via pin 10 (dig2) is enabled note: 1. it is necessary to set register bit irq_2_ext_en (register 0x04, trx_ctrl_1).
155 8351b C C AT86RF233 11.7 frame buffer empty indicator 11.7.1 overview for time critical applications that want to start reading the frame data as early as possible, the atmel at8 6rf233 frame buffer status can be indicated to the microcontroller through a dedicated pin. this pin indi cate s to the microcontroller if an access to the frame buffer is not possible since valid psdu data are missing . pin 24 (irq) can be configured as a frame buffer empty indicator during a frame buffer read access . this mode is enabled by register bit rx_bl_ctrl ( register 0x 04 , trx_ctrl_1 ). the irq pin turns in to frame buffer e mpty indicator after the frame buffer read access command , see note (1) in figure 11 - 25 , has been transferred on the spi bus until the frame buffer read procedure has finished indicated by /sel = h , see note (4) . figure 11 - 25 . timing diagram of frame buffer empty indicator . note s : 1. timing figure t 12 refer to section 12.4 . 2. a frame buffer read access can proceed as long as pin 24 (irq) = l . 3. pin irq = h indicates that the frame buffer is currently not ready for another spi cycle . 4. t he frame buffer read procedure has finished indicated by /sel = h . the microcontroller has to observe the irq pin during the frame buffer read procedure. a frame buffer read access can proceed as long as pin 24 ( irq ) = l, see note (2) . pin irq = h indicates that the frame buffer is currently not ready for another spi cycle, note (3) , and thus the frame buffer read procedure has to w ait for valid data accordingly. the access indicator pin 24 (irq) shows a valid access signal (either access is allowed or denied ) not before t 12 = 750 ns after the rising edge of last sclk clock of the frame buffer read command byte. after finishing the spi frame receive procedure , and the spi has been released by /sel = h , note (4) , pending interrupts are indicated immediately by pin 24 (irq) . during all other spi accesses, except during a spi frame receive procedure with rx_bl_ctrl = 1, pin irq only indicates interrupts. if during the frame buffer read access a receive error occurs ( for example a n pll unlock), the frame buffer empty indicator locks on 'empty' ( pin 24 (irq) = h ) too. to prevent possible deadlocks, the microcontroller s hould impose a timeout counter that checks whether the frame buffer empty indicator remains logic high for more than 64 s . assuming a phy data rate of 250 kb/s , a new byte must have been arrived at the frame buffer during that period. if not, the frame buff er read access should be aborted. / s e l m o s i m i s o i r q s c l k c o m m a n d p h y _ s t a t u s x x i r q _ s t a t u s c o m m a n d t r x _ s t a t u s x x p h r [ 7 : 0 ] x x p s d u [ 7 : 0 ] i r q _ 2 ( r x _ s t a r t ) x x p s d u [ 7 : 0 ] x x p s d u [ 7 : 0 ] t 1 2 x x r x _ s t a t u s c o m m a n d t r x _ s t a t u s x x i r q _ s t a t u s i r q _ 3 ( t r x _ e n d ) f r a m e b u f f e r e m p t y i n d i c a t o r ( 1 ) ( 4 ) ( 3 ) n o t e s ( 2 ) x x l q i [ 7 : 0 ] x x e d [ 7 : 0 ]
156 8351b C C AT86RF233 11.7.2 register description register 0x04 (trx_ctrl_1): the trx_ctrl_1 register is a multi - purpose register to control various operating modes and settings of the radio transceiver. figure 11 - 26 . register trx_ctrl_1. bit 7 6 5 4 0x04 pa_ext_en irq_2_ext_en tx_auto_crc_ on rx_bl_ctrl trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 bit 3 2 1 0 0x04 spi_cmd_mode irq_mask_mode irq_polarity trx_ctrl_1 read/write r/w r/w r/w r/w reset value 0 0 1 0 ? bit 4 - rx_bl_ctrl the register bit rx_bl_ctrl controls the frame buffer empty indicator. table 11 - 22 . rx_bl_ctrl. register bits value description rx_bl_ctrl 0 frame buffer empty indicator disabled 1 frame buffer empty indicator enabled note: 1. a modification of register bit irq_polarity has no influence to rx_bl_ctrl behavior. if this register bit is set, the frame buffer empty indicator is enabled. after sending a frame buffer read command ( refer to section 6.3 ), pin 24 (irq) indicates that an access to the frame buffer is not possible since p sdu data are not available yet. t he p in 24 ( irq ) does not indicate any interrupts during this time.
157 8351b C C AT86RF233 11.8 dynamic frame buffer protection 11.8.1 overview the atmel AT86RF233 continues the reception of incoming frames as long as it is in any receive state. when a frame was successfully received and stored into the frame buffer, the following frame will overwrite the frame buffe r content again. to relax the timing requirements for a frame buffer read access the dynamic frame buffer protection prevents that a new valid frame passes to the frame buffer until a frame buffer read access has ended (indicated by /sel = h, refer to sect ion 6.3 ). a received frame is automatically protected against overwriting : ? in basic operating mode, if its fcs is valid ? in extended operating mode , if an irq_3 ( trx_end ) is generated . the dynamic frame buffer protection is enabled with rx_safe_mode (register 0x0c, trx_ctrl_2) set and applicable transceive r state s rx_on and rx_aack_on. note: 1. the dynamic frame buffer protection only prevents write accesses from the air interface C not from the spi interface. a frame buffer or sram write access may still modify the frame buffer content. 11.8.2 register description register 0x0c (trx_ctrl_2): the trx_ctrl_2 register is a multi - purpose control register to control various settings of the radio transceiver. figure 11 - 27 . register trx_ctrl_2. bit 7 6 5 4 0x0c rx_safe_mode reserved oqpsk_scram_ en reserved trx_ctrl_2 read/write r/w r r/w r reset value 0 0 1 0 bit 3 2 1 0 0x0c reserved oqpsk_data_rate trx_ctrl_2 read/write r r/w r/w r/w reset value 0 0 0 0 ? bit 7 - rx_safe_mode protect frame buffer after frame reception with valid fcf check. table 11 - 23 . rx_safe_mode. register bits value description rx_safe_mode 0 disable dynamic frame buffer protection 1 (1) enable dynamic frame buffer protection note: 1. dynamic frame buffer protection is released with the rising edge of /sel pin of a frame buffer read access, or radio transceiver state changes from rx_on or rx_aack_on to another state. this operation mode is independent of the setting of register bits rx_pdt_level, (register 0x15, rx_syn), refer to section 9.1.3 .
158 8351b C C AT86RF233 11.9 alternate start - of - frame delimiter 11.9.1 overview the sfd is a field indicating the end of the shr and the start of the packet data. the length of the sfd is one octet . th e octet is used for byte synchronization only and is not included in the atmel AT86RF233 frame buffer. the value of the sfd can be changed if it is needed to operate non ieee 802.15.4 compliant networks. an ieee 802.15.4 compliant network node does not synchronize to fra mes with a different sfd value. due to the way the shr is formed, it is not recommended to set the low - order four bits to zero . the lsb of the sfd is transmitted first, that is right after the last bit of the preamble sequence. 11.9.2 register description register 0x0b (sfd_value): the sfd_valu e register contains the one octet start - of - frame delimiter (sfd). figure 11 - 28 . register sfd_value. bit 7 6 5 4 0x0b sfd_value sfd_value read/write r/w r/w r/w r/w reset value 1 0 1 0 bit 3 2 1 0 0x0b sfd_value sfd_value read/write r/w r/w r/w r/w reset value 0 1 1 1 ? bit 7:0 - sfd_value the register bits sfd_value are required for transmit and receive operation. table 11 - 24 . sfd_value. register bits value description sfd_value 0xa7 for transmission this value is copied into start - of - frame delimiter (sfd) field of frame header. for reception this value is checked for incoming frames. the default value is according to ieee 802.15.4 specif ication. for ieee 802.15.4 compliant networks, set sfd_value = 0xa7 as specified in [ 2 ] . this is the default value of the register. to establish non ieee 802.15.4 compliant networ ks, the sfd value can be changed to any other value. if enabled, irq_2 ( rx_start ) is issued only if the received sfd matches sfd_value and a valid phr is re ceived.
159 8351b C C AT86RF233 11.10 reduce d power consumption mode (rpc) the reduced power consumption mode is characterized by: ? significant power reduction for several operating modes ? self - contained, self - calibrating and adaptive power reduction schemes 11.10.1 overview atmel AT86RF233 rpc offers a variety independent techniques and methods to significantly reduce the power consumption . rpc is applicable to several o perating m odes and transparent to other extended features . notes: 1. to achieve the lowest power consumption the register 0x16, trx_rpc setting 0xff. 2. for disabling the reduced power consumption mode s set register 0x16, trx_rpc to 0xc1 or 0x01 . 11.10.2 rpc methods and elements 11.10.2.1 pes C pll energy saving the pes mode is activated with register bit pll_rpc_en ( register 0x 16, trx_rpc) set to one . applicable to states: pll_on and tx_aret_on a state change towards pll_on or tx_aret_on causes an initial pll calibration run , immediately followed by entering the pes mode . a state change towards rx or tx states, a channel switch or pll calibration causes a pll wake - up . after finishing such an operation, the pll automatically enters the pes mode. the typical c urrent consumption i pll_on reduces from 5.2 ma to 450 a . 11.10.2.2 srt C smart receiving technology the srt mode is activated with register bit rx_rpc_en ( register 0x 16, trx_rpc) set to one. applicable to states: rx_on, rx_aack_on and tx_aret srt redu ces the average power consumption during rx listening periods . in typical environment situations srt reduces the average current consumption i rx_on by up t o 50%. a configuration of srt is done with register bits rx_rpc_ctrl ( register 0x 16, trx_rpc) . note s : 1. its recommended to disable srt during rssi measurements or rnd generation. 2. during cca or/and ed scan the srt is disable d automatically. 3. if autonomous antenna diversity is enabled, srt cannot achieve the maximum effect. 4. depending on operating conditions (traffic, temperature, channel noise, frequency settings) the effective reduct ion of current consumption may vary .
160 8351b C C AT86RF233 11.10.2.3 erd C extended receiver desensitiz ing atmel AT86RF233 erd is activated with register bit pdt_rpc_en ( register 0x 16, trx_rpc) set to one. applicable to states: rx, rx_aack and tx_aret in combination with rx_pdt_level settings, the average rx current is further significantly reduced, for details refer to section 12.8 . an rx_pdt_level = 0x08 setting requires special attention. in contrast to definitions in table 9 - 3 , the sensitivity is reduced to - 80 db m only, but at much lower average rx listen current than comparable register settings. notes: 1. with rx_pdt_level = 0x08, rssi/ed can not resolve rx input levels from - 80 db m to - 67 db m. 2. during cca or/and ed scan the erd is disable d automatically. 11.10.2.4 tph C automated tx power h andling tph is activated with register bit xah_tx_rpc_en ( register 0x 16, trx_rpc) set to one. applicable to states: rx_aack ack frame tx output power setting is automatically adapted according to a combination of received rx frame ed and lqi value s . if a n expected frame has been successfully received with ed > - 77 db m and lqi > 224, the tx output power is reduced. the minimum power is - 17 db m (ed > - 45 db m and lqi > 224 ), whereas the maximum is set be register bits tx_pwr (register 0x05, phy_tx_pwr) . reading the tx_pwr field provides the used transmit power for last transmitted frame including acknowledgement frame. this allows monitoring the actual rpc handling used for transmitting. see register bit s tx_pwr description for further information. the table 11 - 25 shows the typical current consumption for dedicated tx output power values. table 11 - 25 . tx o utput p ower versus c urrent c onsumption (extraction) . register bits tx output power [dbm] current consumption [ma] tx_pwr +4 13.8 +0 11.8 - 17 7.2 notes: 1. the upper limit will be declared by register bits tx_pwr (register 0x05, phy_tx_pwr), refer to section 9.2.5 . 2. if the sequence number, refer to section 8.1.2 , from previous received frame equal to the current frame sequence number, then no automatic tx power reduction will be activated. applicable to states: tx_aret if the first frame transmission fails, using a reduced tx output power as set by register bits tx_pwr (register 0x05, phy_tx_pwr) , the next frame retry starts with maximum tx output power ( +4 dbm ) .
161 8351b C C AT86RF233 note: 3. the l ower limit for the first frame transmitting will be declared by register bits tx_pwr (register 0x05, phy_tx_pwr ) , refer to section 9.2.5 . achievable tx current consumption i busy_tx reductions are shown in section 12.8 or table 11 - 25 . 11.10.2.5 p am C pan address match recognition atmel AT86RF233 pam is activated with register bit ipan_rpc_en ( register 0x 16, trx_rpc) set to one. applicable to states: rx_aack address match fail indication of the ieee 802.15.4 frame filtering causes stopping of the receive procedure in two ways: 1. if pan address does not match , a new listen period starts immediately , 2. if pan address matches , the radio transceiver enters power saving mode for remaining frame and ack period, if an ack is requested. notes: 1. pam is applicable to short ack time and reserved frames types as set by register bit aack_ack_time and register bit aack_fltr_res_ft ( register 0x17, xah_ctrl_1 ) , respectively. 2. if promiscuous mode is enabled with aack_prom_mode ( register 0x17, xah_ctrl_1) set, pam is disabled automatically . 11.10.2.6 miscellaneous power reduction functions applicable to states: rx and rx_aack in addition to dynamic frame buffer protection, refer to section 11.8 : during dynamic frame buffer protection , the radio transceiver automatically enters the power save mode . applicable to states: tx_aret in addition to csma - ca retry , refer to section 7.2.4 : after starting the tx_aret transaction, a random backoff period is performed. within this backoff period the radio transceiver automatically enters power saving mode . applicable to states: tx_aret and rx_aack in addition to tx/rx turnaround time , refer to section 7.2 : t he radio transceiver automatically enters power saving mode in: ? tx_aret: during the ti me waiting for an ack frame, or ? rx_aack: during the time waiting for ack transmission note: 1. to handle nodes configured with a rx/tx turnaround time less than 12 symbols, register bits are to be set to rx_rpc_ctrl = 0 within tx_aret . alternatively, register bit aack_ack_time (register 0x17, xah_ctrl_1) can be set to one.
162 8351b C C AT86RF233 11.10.3 register summary register 0x16 (trx_rpc): the trx_rpc register controls the reduce power consumption modes. figure 11 - 29 . register trx_rpc. bit 7 6 5 4 0x16 rx_rpc_ctrl rx_rpc_en pdt_rpc_en trx_rpc read/write r/w r/w r/w r/w reset value 1 1 0 0 bit 3 2 1 0 0x16 pll_rpc_en xah_tx_rpc_en ipan_rpc_en reserved trx_rpc read/write r/w r/w r/w r/w reset value 0 0 0 1 note: 1. the reserved bit needs to be set one for write access. ? bit 7:6 - rx_rpc_ctrl the register bits rx_rpc_ctrl are used for internal performance settings within smart receiving mode. table 11 - 26 . rx_rpc_ctrl. register bits value description rx_rpc_ctrl 0 activates minimum power saving behavior for smart receiving mode 3 activates maximum power saving behavior for smart receiving mode all other values are reserved ? bit 5 - rx_rpc_en the register bit rx_rpc_en activates the smart receiving mode for all rx listening modes. table 11 - 27 . rx_rpc_en. register bits value description rx_rpc_en 0 smart receiving mode is disabled 1 smart receiving mode is enabled ? bit 4 - pdt_rpc_en the register bit pdt_rpc_en controls in combination with the rx_pdt_level value the reduced sensitivity behavior under the rpc mode. table 11 - 28 . pdt_rpc_en. register bits value description pdt_rpc_en 0 the reduced sensitivity rpc mode is disabled 1 the reduced sensitivity rpc mode is enabled
163 8351b C C AT86RF233 ? bit 3 - pll_rpc_en the register bit pll_rpc_en controls the extended pll behavior within pll_on and tx_aret_on modes. table 11 - 29 . pll_rpc_en. register bits value description pll_rpc_en 0 the extended pll behavior is disabled 1 the extended pll behavior is enabled ? bit 2 - xah_tx_rpc_en the register bit xah_tx_rpc_en controls in combination with the tx_pwr value the automatic tx power handling within the extended operating mode. table 11 - 30 . xah_tx_rpc_en. register bits value description xah_tx_rpc_en 0 the automatic tx power handling is disabled 1 the automatic tx power handling is enabled ? bit 1 - ipan_rpc_en the register bit ipan_rpc_en controls the own pan handling within the rpc mode. table 11 - 31 . ipan_rpc_en. register bits value description ipan_rpc_en 0 the rpc pan handling is disabled 1 the rpc pan handling is enabled
164 8351b C C AT86RF233 12 electrical characteristics 12.1 absolute maximum ratings note : stresses beyond those listed under Dabsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter condition min. typ. max. unit t stor storage temperature - 50 150 c t lead lead temperature t = 10s (soldering profile compliant with ipc/jedec j std 020b) 260 c v esd esd robustness human body model (hbm) [4], 4 kv charged device model (cdm) [5] 750 v p rf input rf level +10 dbm v dig voltage on all pins (except pins 4, 5, 13, 14, 29) - 0.3 v dd +0.3 v v ana voltage on pins 4, 5, 13, 14, 29 - 0.3 2.0 v 12.2 recommended operating range symbol parameter condition min. typ. max. unit t op operating temperature range - 40 +25 +85 c v dd supply voltage voltage on pins 15, 28 (1) 1.8 3.0 3.6 v v dd1.8 supply voltage (on pins 13, 14, 29) external voltage supply (2) 1.7 1.8 1.9 v notes: 1. even if an implementation uses the external 1.8v voltage supply v dd1.8 it is required to connect v dd . 2. register 0x10 (vreg_ctrl) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8v supply, refer to section 9.4. caution! esd sensitive device. precaution should be used when handling the device in order to prevent permanent damage.
165 8351b C C AT86RF233 12.3 digital pin characteristics test conditions: t op = +25 c (unless otherwis e stated ) . symbol parameter condition min. typ. max. unit v ih high level input voltage (1) v dd - 0.4 v v il low level input voltage (1) 0.4 v v oh high level output voltage (1) v dd - 0.4 v v ol low level output voltage (1) 0.4 v c load capacitive load (1) 50 pf note: 1. the capacitive load c load should not be larger than 50pf for all i/os. generally, large load capacitances increase the overall current consumption. 12.4 digital interface timing characteristics test conditions: t op = +25 c , v dd = 3.0 v , c l oad = 50 pf (unless otherwise sta ted) . symbol parameter condition min. typ. max. unit f sync sclk frequency synchronous operation 8 mhz f async sclk frequency asynchronous operation 7.5 mhz t 1 /sel falling edge to miso active 180 ns t 2 sclk falling edge to miso out data hold time 25 ns t 3 mosi setup time 10 ns t 4 mosi hold time 10 ns t 5 lsb last byte to msb next byte spi read/write, standard sram and frame access modes 250 (1) ns t 5a lsb last byte to msb next byte fast sram read/write access mode 500 (1) ns t 6 /sel rising edge to miso tri state 10 ns t 7 slp_tr pulse width tx start trigger 62.5 note (2) ns t 8 spi idle time: sel rising to falling edge spi read/write, standard sram and frame access modes idle time between consecutive spi accesses 250 (1) ns t 8a spi idle time: sel rising to falling edge fast sram read/write access mode idle time between consecutive spi accesses 500 (1) ns t 9 last sclk rising edge to /sel rising edge 250 ns t 10 reset pulse width 10 clock cycles at 16mhz 625 ns t 11 spi access latency after reset 10 clock cycles at 16mhz 625 ns t 12 frame buffer empty indicator latency rising edge of last sclk clock of the frame buffer read command byte to rising edge of irq 750 ns t irq irq_2, irq_3, irq_4 latency relative to the event to be indicated 9 s f clkm output clock frequency at pin 17 (clkm) configurable in register 0x03 0 mhz
166 8351b C C AT86RF233 symbol parameter condition min. typ. max. unit clkm_ctrl = 0 clkm_ctrl = 1 1 mhz clkm_ctrl = 2 2 mhz clkm_ctrl = 3 4 mhz clkm_ctrl = 4 8 mhz clkm_ctrl = 5 16 mhz clkm_ctrl = 6 250 khz clkm_ctrl = 7 62.5 khz notes: 1. for fast sram read/write accesses on address space 0x82 C 0x94 the time t 5 (min.) and t 8 (min.) increases to 500ns. 2. maximum pulse width less than (tx frame length + 16s). 12.5 general rf specifications test conditions (unless otherwise stated) : v dd = 3.0 v , f rf = 2445 mhz , t op = +25 c , measurement setup see figure 5 - 1 . symbol parameter condition min. typ. max. unit f rf frequency range as specified in [1], [2] 2405 2445 2480 mhz 500khz spacing 2322 2527 mhz f ch channel spacing as specified in [1], [2] 5 mhz 500khz spacing 500 khz f hdr header bit rate (shr, phr) as specified in [1], [2] 250 kb/s f psdu psdu bit rate as specified in [1], [2] 250 kb/s oqpsk_data_rate = 1 500 kb/s oqpsk_data_rate = 2 1000 kb/s oqpsk_data_rate = 3 2000 kb/s f chip chip rate as specified in [1], [2] 2000 kchip/s f clk crystal oscillator frequency reference oscillator 16 mhz f srd symbol rate deviation reference frequency accuracy for correct functionality psdu bit rate 250kb/s - 60 (1) +60 ppm 500kb/s - 40 +40 ppm 1000kb/s - 40 +40 ppm 2000kb/s - 30 +30 ppm f 20db 20db bandwidth 2.8 mhz note: 1. a reference frequency accuracy of 40ppm is required by [1], [2].
167 8351b C C AT86RF233 12.6 transmitter characteristics test condit ions (unless otherwise stated): v dd = 3.0 v , f rf = 2445 mhz , t op = +25 c , measurement setup see figure 5 - 1 . symbol parameter condition min. typ. max. unit p tx_max tx output power maximum configurable tx output power value register bit tx_pwr = 0 +4 dbm p range output power range 16 steps, configurable in register 0x05 (phy_tx_pwr) 21 db p acc output power tolerance 2 db evm error vector magnitude 12 %rms p harm harmonics 2 nd harmonic - 40 dbm 3 rd harmonic - 45 dbm p spur_tx spurious emissions (1) 30 C 1000mhz - 36 dbm >1 C 12.75ghz - 30 dbm 1.8 C 1.9ghz - 47 dbm 5.15 C 5.3ghz - 47 dbm note: 1. complies with en 300 328/440, fcc - cfr - 47 part 15, arib std - 66, rss - 210. 12.7 receiver characteristics test condit ions (unless otherwise stated): v dd = 3.0 v , f rf = 2445 mhz , t op = +25 c , f psdu = 250 kb/s , measurement setup see figure 5 - 1 . symbol parameter condition min. typ. max. unit p sens receiver sensitivity 250kb/s (1) - 101 dbm 500kb/s (1) - 96 dbm 1000kb/s (1) - 94 dbm 2000kb/s (1) - 88 dbm antenna diversity 250kb/s (1) - 98 dbm smart receiving 250kb/s (1) - 100 dbm rl rx rx return loss 100 differential impedance 10 db nf noise figure 6 db p rx_max maximum rx input level 250kb/s (1) 8 dbm p acrn adjacent channel rejection: - 5mhz p rf = - 82dbm (1) 32 db p acrp adjacent channel rejection: +5mhz p rf = - 82dbm (1) 35 db p aacrn adjacent channel rejection: - 10mhz p rf = - 82dbm (1) 48 db p aacrp adjacent channel rejection: p rf = - 82dbm (1) 48 db
168 8351b C C AT86RF233 symbol parameter condition min. typ. max. unit +10mhz p aacr2n 2 nd alternate channel rejection: - 15mhz p rf = - 82dbm (1) 54 db p aacr2p 2 nd alternate channel rejection: +15mhz p rf = - 82dbm (1) 54 db p spur_rx spurious emissions lo leakage - 70 dbm 30 C 1000mhz - 57 dbm >1 C 12.75ghz - 47 dbm f car_offs tx/rx carrier frequency offset sensitivity loss 2db - 300 (2) +300 khz iip3 3 rd C order intercept point at maximum gain offset freq. interf. 1 = 5mhz offset freq. interf. 2 = 10mhz - 10 dbm iip2 2 nd C order intercept point at maximum gain offset freq. interf. 1 = 60mhz offset freq. interf. 2 = 62mhz 31 dbm rssi tol rssi tolerance tolerance within gain step 5 db rssi range rssi dynamic range 87 db rssi res rssi resolution 3 db rssi base_v al rssi sensitivity defined as rssi_base_val - 91 dbm rssi min minimum rssi value p rf rssi_base_val 0 rssi max maximum rssi value p rf rssi_base_val + 84db 28 notes: 1. awgn channel, per 1%, psdu length 20 octets. 2. offset equals 120ppm. 12.8 current consumption specifications test condit ions (unless otherwise stated): v dd = 3.0 v , f rf = 2445 mhz , t op = +25 c , measurement setup see figure 5 - 1 . symbol parameter condition min. typ. max. unit i busy_tx supply current transmit state p tx = +4dbm 13.8 ma p tx = +0dbm 11.8 ma p tx = - 17dbm 7.2 ma i rx_on supply current rx_on state high sensitivity rx_pdt_level = [0x0] 11.8 ma active rpc mode (2) will further reduce current consumptions i rx_on_l0 supply current rx_on state with active receiver desensitize receiver desensitize rx_pdt_level = [0x1, ..., 0xe, 0xf] (1) 11.3 ma active rpc mode (2) will further reduce current consumptions; using rx_pdt_level = [0x8, ..., 0xe, 0xf] (1) reduces current
169 8351b C C AT86RF233 symbol parameter condition min. typ. max. unit consumption further by about 1ma i pll_on supply current pll_on state 5.2 ma with active rpc mode (2) 450 a i trx_off supply current trx_off state 300 a i sleep supply current sleep state 0.2 a i deep_sleep supply current deep_sleep state 0.02 a notes: 1. refer to section 9.1. 2. refer to section 11.10 . 3. all power consumption measurements are performed with clkm disabled. 12.9 crystal parameter requirements test conditions: t op = +25 c , v dd = 3.0 v (unless otherwise stated) . symbol parameter condition min. typ. max. unit f 0 crystal frequency 16 mhz c l load capacitance 8 14 pf c 0 crystal shunt capacitance 7 pf esr equivalent series resistance 100
170 8351b C C AT86RF233 13 typical characteristics 13.1 active supply current the following charts showing each a typical behavior of the atmel AT86RF233 . these figures are not tested during manufacturing. all power consumption measurements are performed with pin 17 (c lkm) disabled, unless otherwise stated. the measurement setup used for the measurements is shown in figure 5 - 1 . the p ower consumption of the microcontroller , which is required to program the radio transceiver, is not included in the measurement results. the p ower consumption in sleep and deep_sleep state is independent from clkm master clock rate selection. the current consumption depends on several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, and ambient temperature. the dominating factors are operating voltage and ambient temperature. if possible the measurement results are not affected by current drawn from i/o pins. register, sram or frame buffer read or write accesses are not performed during current consumption measurements. 13.1.1 p_on and trx_off states figure 13 - 1 . current consumpt ion in p_on state .
171 8351b C C AT86RF233 figure 13 - 2 . current consumption in trx_off state . 13.1.2 pll_on state figure 13 - 3 . current consumption in pll_on state .
172 8351b C C AT86RF233 13.1.3 rx_on state figure 13 - 4 . current consumption in rx_on state C high sensitivity . figure 13 - 5 . current consumption in rx_on state C high input level .
173 8351b C C AT86RF233 figure 13 - 6 . current consumption in rx_on state C reduced sensitivity . 13.1.4 tx_busy state figure 13 - 7 . current consumption in tx_busy state C minimum output power .
174 8351b C C AT86RF233 figure 13 - 8 . current consumption in tx_busy state C output power 0 db m . figure 13 - 9 . current consumption in tx_busy state C maximum output power .
175 8351b C C AT86RF233 13.1.5 sleep figure 13 - 10 . current consumption in sleep . 13.1.6 deep_sleep figure 13 - 11 . current consumption in deep_sleep .
176 8351b C C AT86RF233 13.2 state transition timing figure 13 - 12 . transition time from evdd to p_on (clkm available) . figure 13 - 13 . transition time from sleep to trx_off ( irq_4 (awake_end) ) .
177 8351b C C AT86RF233 figure 13 - 14 . transition time from trx_off to pll_on .
178 8351b C C AT86RF233 14 register reference the atmel AT86RF233 provides a register space of 64 8 - bit registers used to configure, control and monitor the radio transceiver. note: all registers n ot mentioned within the following table are reserved for internal use and must not be overwritten. when writing to a register, any reserved bits shall be overwritten only with their reset value. table 14 - 1 . register summary . addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x01 trx_status cca_done cca_status reserved trx_status 43 , 64 , 96 0x02 trx_state trac_status trx_cmd 44 , 65 0x03 trx_ctrl_0 reserved reserved reserved reserved clkm_sha_sel clkm_ctrl 118 0x04 trx_ctrl_1 pa_ext_en irq_2_ext_en tx_auto_crc_on rx_bl_ctrl spi_cmd_mode irq_mask_mode irq_polarity 21 , 29 , 67 , 88 , 152 , 153 , 156 0x05 phy_tx_pwr reserved reserved reserved tx_pwr 105 0x06 phy_rssi rx_crc_valid rnd_value rssi 88 , 90 , 138 0x07 phy_ed_level ed_level 93 0x08 phy_cc_cca cca_request cca_mode channel 97 , 123 0x09 cca_thres reserved cca_ed_thres 98 0x0a rx_ctrl reserved reserved reserved pdt_thres 148 0x0b sfd_value sfd_value 158 0x0c trx_ctrl_2 rx_safe_mode reserved oqpsk_scram_en reserved oqpsk_data_rate 143 , 157 0x0d ant_div ant_sel reserved ant_div_en ant_ext_sw_en ant_ctrl 148 0x0e irq_mask irq_mask 28 0x0f irq_status irq_7_bat_low irq_6_trx_ur irq_5_ami irq_4_cca_ed_done irq_3_trx_end irq_2_rx_start irq_1_pll_unlock irq_0_pll_lock 28 0x10 vreg_ctrl avreg_ext avdd_ok reserved dvreg_ext dvdd_ok reserved 111 0x11 batmon reserved reserved batmon_ok batmon_hr batmon_vth 114 0x12 xosc_ctrl xtal_mode xtal_trim 119 0x13 cc_ctrl_0 cc_number 1 24 0x14 cc_ctrl_1 reserved cc_band 125 0x15 rx_syn rx_pdt_dis reserved rx_pdt_level 102 , 144 0x16 trx_rpc rx_rpc_ctrl rx_rpc_en pdt_rpc_en pll_rpc_en xah_tx_rpc_en ipan_rpc_en reserved 162 0x17 xah_ctrl_1 aret_tx_ts_en reserved aack_fltr_res_ft aack_upld_res_ft reserved aack_ack_time aack_prom_mode aack_spc_en 68 , 144 , 154 0x18 ftn_ctrl ftn_start reserved reserved 127 0x19 xah_ctrl_2 aret_frame_retries aret_csma_retries reserved 70 0x1a pll_cf pll_cf_start reserved reserved pll_cf 125 0x1b pll_dcu pll_dcu_start reserved reserved 126 0x1c part_num part_num 22 0x1d version_num version_num 22 0x1e man_id_0 man_id_0 23 0x1f man_id_1 man_id_1 23 0x20 short_addr_0 short_addr_0 76 0x21 short_addr_1 short_addr_1 76 0x22 pan_id_0 pan_id_0 76 0x23 pan_id_1 pan_id_1 77 0x24 ieee_addr_0 ieee_addr_0 77 0x25 ieee_addr_1 ieee_addr_1 77 0x26 ieee_addr_2 ieee_addr_2 78 0x27 ieee_addr_3 ieee_addr_3 78 0x28 ieee_addr_4 ieee_addr_4 78
179 8351b C C AT86RF233 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x29 ieee_addr_5 ieee_addr_5 79 0x2a ieee_addr_6 ieee_addr_6 79 0x2b ieee_addr_7 ieee_addr_7 79 0x2c xah_ctrl_0 max_frame_retries max_csma_retries slotted_operation 71 0x2d csma_seed_0 csma_seed_0 72 0x2e csma_seed_1 aack_fvn_mode aack_set_pd aack_dis_ack aack_i_am_coord csma_seed_1 73 0x2f csma_be max_be min_be 75 0x36 tst_ctrl_digi reserved reserved reserved reserved tst_ctrl_dig 187
180 8351b C C AT86RF233 the reset values of the atmel AT86RF233 register s in state p_on (1 , 2, 3 ) are shown in table 14 - 2 . note: all reset values in table 14 - 2 are only valid after a power on reset. after a reset procedure (/rst = l) as described in section 7.1.4.6 , the reset values of selected registers ( for example registers 0x01, 0x10, 0x11 , 0x30 ) can differ from that in table 14 - 2 . table 14 - 2 . register summary C reset values . address reset value 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x09 0x04 0x22 0x05 0x00 0x06 0x60 0x07 0xff 0x08 0x2b 0x09 0xc7 0x0a 0x37 0x0b 0xa7 0x0c 0x20 0x0d 0x00 0x0e 0x00 0x0f 0x00 address reset value 0x10 0x00 0x11 0x02 0x12 0xf0 0x13 0x00 0x14 0x00 0x15 0x00 0x16 0xc1 0x17 0x00 0x18 0x58 0x19 0x00 0x1a 0x57 0x1b 0x20 0x1c 0x0b 0x1d 0x01 0x1e 0x1f 0x1f 0x00 address reset value 0x20 0xff 0x21 0xff 0x22 0xff 0x23 0xff 0x24 0x00 0x25 0x00 0x26 0x00 0x27 0x00 0x28 0x00 0x29 0x00 0x2a 0x00 0x2b 0x00 0x2c 0x38 0x2d 0xea 0x2e 0x42 0x2f 0x53 address reset value 0x30 0x00 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x00 0x35 0x00 0x36 0x00 0x37 0x00 0x38 0x00 0x39 0x40 0x3a 0x00 0x3b 0x00 0x3c 0x00 0x3d 0x00 0x3e 0x00 0x3f 0x00 notes: 1. while the reset value of register 0x10 is 0x00, any practical access to the register is only possible when dvreg is active. so this register is always read out as 0x04. for details, refer to section 9.4 . 2. while the reset value of register 0x11 is 0x02, any practical access to the register is only possible when batmon is activated. so this register is always read out as 0x22 in p_on state. for details, refer to section 9.5 . 3. while the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the radio transceiver is accessible. so the register is usually read out as: a) 0x11 after a reset in p_on state b) 0x07 after a reset in any other state
181 8351b C C AT86RF233 15 abbreviations a ack automatic acknowledgement ack acknowledgement adc analog - to - d igital c onverter ad antenna diversity aes advanced e ncryption s tandard agc automatic g ain c ontrol aret automatic retrans mission avreg analog voltage regulator awgn additive white gaussian noise batmon battery monitor bbp base - band processor bpf band - pass filter cbc cipher block chaining cca clear channel assessment cc current channel cf center frequency crc cyclic redundancy check cs carrier sense csma - ca carrier sense multiple access C collision avoidance cw continuous wave dvreg digital voltage regulator ecb electronic code book ed energy detect esd electros tatic d ischarge evm error v ector m agnitude f c channel center frequency fcf frame control field fcs frame check sequence fifo first in, first out ftn filter tuning network gpio general purpose input/output ic integrated circuit ieee institute of electrical and electronic engineers if intermediate frequency irq interrupt request ism industrial scientific medical ldo low dropout lna low - noise amplifier lo local oscillator lpf low - pass filter lqi link quality indi cation lsb least significant bit mac medium access control mfr mac f ooter mhr mac header mic message integrity code miso master input, slave output mosi master output, slave input msb most significant bit msdu mac service data unit mpdu mac p rotocol d ata u nit msk minimum s hift k eying
182 8351b C C AT86RF233 nop no operation o - qpsk offset quadrature phase shift keying pa power amplifier pan personal area network pcb printed c ircuit b oard per packet error rate phr phy header phy physical layer pll phase - looked loop ppdu phy protocol data unit ppf poly - phase filter prbs pseudo random binary sequence psd power spectrum density psdu phy service data unit qfn quad flat no - lead package rf ra dio frequency rssi received signal strength indicator rx receiver sfd start - of - frame delimiter shr synchronization header spi serial peripheral interface sram static random access memory srd short range device ssbf single s ide band f ilter trx transceiver tx transmitter vco voltage controlled oscillator wpan wireless personal area network xosc crystal oscillator xtal crystal
183 8351b C C AT86RF233 16 ordering information ordering code packaging package voltage range temperature range AT86RF233 - z u tray qn 1.8 v C 3.6 v industrial ( - 40 c to +85 c ) lead - free/halogen - free AT86RF233 - z ur tape & reel qn 1.8 v C 3.6 v industrial ( - 40 c to +85 c ) lead - free/halogen - free package type description qn 32qn2 , 32 - lead 5.0x5.0mm body, 0.50 mm pitch, quad flat no - lead package (qfn) sawn note: t& r quantity 5 ,000. please contact your local atmel sales office for more detailed ordering information and minimum quantities. 17 soldering information recommended soldering profile is specified in ipc/jedec j - std - .020c. 18 package thermal properties thermal resistance velocity [m/s] theta ja [k/w] 0 40.9 1 35.7 2.5 32.0
184 8351b C C AT86RF233 19 package drawing C 32qn 2 s y m b o l m i n . n o m . m a x . n o t e
185 8351b C C AT86RF233 appendix a - continuous transmission test mode a.1 - overview the atmel AT86RF233 offers a continuous transmission test mode to support final application / production tests as well as certification tests. using this test mode the radio transceiver transmits continuously a previously transferred frame (prbs mode) or a continuous wave si gnal (cw mode). in cw mode two different signal frequencies per channel can be transmitted: ? f 1 = fc + 0.5 mhz ? f 2 = fc - 0.5 mhz here fc is the channel center frequency , refer to section 9.7.2 . note: 1. in cw mode it is not possible to transmit a rf signal directly on the channel center frequency. psdu d ata in the frame buffer must contain at least a valid phr (see sec tion 8.1 ). it is recommended to use a frame of maximum length (127 bytes) and arbitrary psdu data for the prbs mode . the shr and the phr are not transmitted. the transmission starts with the psdu data and is repeated continuously . a.2 - configuration before enabling continuous transmission test mode all register configurations shall be done as follow: ? tx channel settin g (optional) ? tx output power setting (optional) ? mode selection (prbs / cw) a register access to register 0x 36 and 0x1c enables the continuous transmission test mode. the transmission is started by enabling the pll (trx_cmd = pll_on) and writing the tx_star t command to register 0x 02. even for cw signal transmission it is required to write valid psdu data to the frame buffer. for prbs mode it is recommended to write a frame of maximum length. the detailed programming sequence is shown in table a - 0 - 1 . the column r/w informs about writing (w) or reading (r) a register or the frame buffer. table a - 0 - 1 . continuous transmission programming sequence . step action register r/w value description 1 reset reset AT86RF233 2 register access 0x0e w 0x01 set irq mask register, enable irq_0 ( pll_lock ) 3 register access 0x04 w 0x00 disable tx_auto_crc_on 4 register access 0x02 w 0x03 set radio transceiver state trx_off 5 register access 0x03 w 0x01 set clock at pin 17 (clkm) 6 register access 0x08 w 0x33 set ieee 802.15.4 channel , for example channel 19
186 8351b C C AT86RF233 step action register r/w value description 7 register access 0x05 w 0x00 set tx output power , for example to p tx_max 8 register access 0x01 r 0x08 verify trx_off state 9 register access 0x36 w 0x0f enable continuous transmission test mode C step # 1 10 (1) register access 0x0c w 0x03 enable raw data mode 11 (1) register access 0x0a w 0x 3 7 enable raw data mode 12 ( 2 ) frame buffer write access w write psdu data (even for cw mode), refer to table a - 0 - 2 13 register access 0x1c w 0x54 enable continuous transmission test mode C step # 2 14 register access 0x1c w 0x46 enable continuous transmission test mode C step # 3 15 register access 0x02 w 0x09 enable pll_on state 16 interrupt event 0x0f r 0x01 wait for irq_0 ( pll_lock ) 17 register access 0x02 w 0x02 initiate transmission, enter busy_tx state 18 measurement perform measurement 19 register access 0x1c w 0x00 disable continuous transmission test mode 20 reset reset AT86RF233 notes: 1. only required for cw mode, do not configure for prbs mode. 2. frame buffer content varies for different modulation schemes. the content of the frame buffer has to be defined for continuous transmission prbs mode or cw mode. to measure the power spectral density (psd) mask of the transmitter it is recommended to use a random sequence of maximum length for the psdu data. to measu re cw signals it is necessary to write either 0x00 or 0xff to the frame buffer, for details refer to table a - 0 - 2 . table a - 0 - 2 . frame buffer content for various continuous transmission modulation schemes . step action frame content comment 12 frame buffer access random sequence m odulated rf signal 0x00 (each byte of psdu ) fc C 0.5 mhz , cw signal 0xff (each byte of psdu ) fc + 0.5 mhz , cw signal note: 1. it is recommended to use a frame of maximum length (127 bytes).
187 8351b C C AT86RF233 a.3 C register description register 0x36 (tst_ctrl_digi): the tst_ctrl_dig register enables the continuous transmission test mode. figure 0 - 1 . register tst_ctrl_digi. bit 7 6 5 4 0x36 reserved tst_ctrl_digi read/write r/w r/w r/w r/w reset value 0 0 0 0 bit 3 2 1 0 0x36 tst_ctrl_dig tst_ctrl_digi read/write r/w r/w r/w r/w reset value 0 0 0 0 ? bit 3:0 - tst_ctrl_dig the register bits tst_ctrl_dig with value 0xf enables continuous transmission. table 0 - 3 . tst_ctrl_dig. register bits value description tst_ctrl_dig 0x0 no mode is active 0xf continuous transmission enabled all other values are reserved
188 8351b C C AT86RF233 appendix b - errata AT86RF233 rev. a potential long pll settling duration in very rare cases a pll_lock interrupt is not generated within the specified max imum t pll_init = 250 s pll lock duration. problem fix/workaround in such a case perform the following action: - read the register bits pll_cf (register 0x1a, pll_cf) - invert the lsb bit - write the value back to the pll_cf register ; keep upper four bits as read before - wait a additional typical t pll_init = 80 s duration or until interrupt is generated
189 8351b C C AT86RF233 references [ 1 ] ieee standard 802.15.4 ? ? ieee standard 802.15.4? C C C C C
190 8351b C C AT86RF233 data sheet revision history rev. 8351b C mcu wireless C 06/12 1. editorial updates 2. update rx_listen description on front page 3. update note 4 on page 159 4. update section 12.8 on page 168 rev. 8351a C mcu wireless C 02/12 1. initial release
191 8351b C C AT86RF233 table of contents 1 pin - out diagram ................................ ................................ .................. 2 1.1 pin descriptions ................................ ................................ ................................ ...... 3 1.2 analog and rf pins ................................ ................................ ............................... 4 1.2.1 supply and ground pins ................................ ................................ ................................ 4 1.2.2 rf pins ................................ ................................ ................................ .......................... 4 1.2.3 crystal oscillator pins ................................ ................................ ................................ ... 5 1.2.4 analog pin summary ................................ ................................ ................................ ..... 5 1.3 digital pins ................................ ................................ ................................ .............. 6 1.3.1 driver str ength settings ................................ ................................ ................................ 6 1.3.2 pull - up and pull - down configuration ................................ ................................ ............. 6 2 disclaimer ................................ ................................ ............................ 7 3 overview ................................ ................................ .............................. 7 4 general circuit desc ription ................................ ................................ 8 5 application schematic ................................ ................................ ..... 10 5.1 basic application schematic ................................ ................................ ................ 10 5.2 extended feature set application schematic ................................ ...................... 12 6 microcontroller interface ................................ ................................ .. 14 6.1 overview ................................ ................................ ................................ ............... 14 6.2 spi timing description ................................ ................................ ......................... 15 6.3 spi protocol ................................ ................................ ................................ .......... 16 6.3.1 register a ccess mode ................................ ................................ ................................ . 16 6.3.2 frame buffer access mode ................................ ................................ ......................... 17 6.3.3 sram access mode ................................ ................................ ................................ .... 19 6.4 radio transceiver status information ................................ ................................ .. 21 6.4.1 register description ................................ ................................ ................................ .... 21 6.5 radio transceiver identification ................................ ................................ ........... 22 6.5.1 register description ................................ ................................ ................................ .... 22 6.6 sleep/wake - up and transmit signal (slp_tr) ................................ ................... 24 6.7 interrupt logic ................................ ................................ ................................ ....... 26 6.7.1 overview ................................ ................................ ................................ ..................... 26 6.7.2 interrupt mask modes and pin polarity ................................ ................................ ........ 27 6.7.3 register description ................................ ................................ ................................ .... 28 7 operating modes ................................ ................................ ............... 31 7.1 basic oper ating mode ................................ ................................ .......................... 31 7.1.1 state control ................................ ................................ ................................ ............... 32 7.1.2 basic operating mode description ................................ ................................ .............. 32 7.1.3 interrupt handling ................................ ................................ ................................ ........ 36 7.1.4 basic operating mode timing ................................ ................................ ..................... 37 7. 1.5 register description ................................ ................................ ................................ .... 43 7.2 extended operating mode ................................ ................................ ................... 45 7.2.1 state control ................................ ................................ ................................ ............... 47 7.2.2 configuration ................................ ................................ ................................ ............... 48
192 8351b C C AT86RF233 7.2.3 rx_aac k_on C receive with automatic ack ................................ ........................... 49 7.2.4 tx_aret_on C transmit with automatic frame retransmission and csma - ca retry ................................ ................................ ................................ ................................ ............. 60 7.2.5 interrupt handling ................................ ................................ ................................ ........ 63 7.2.6 register summary ................................ ................................ ................................ ....... 64 7.2.7 regi ster description C control registers ................................ ................................ ..... 64 7.2.8 register description C address registers ................................ ................................ ... 76 8 functional description ................................ ................................ ..... 80 8.1 introduction C ieee 802.15.4 - 2006 frame format ................................ .............. 80 8.1.1 phy protocol data unit (ppdu) ................................ ................................ .................. 80 8.1.2 mac protocol data unit (mpdu) ................................ ................................ ................ 82 8.2 frame check sequence (fcs) ................................ ................................ ............ 86 8.2.1 overview ................................ ................................ ................................ ..................... 86 8.2.2 crc calculat ion ................................ ................................ ................................ .......... 86 8.2.3 automatic fcs generation ................................ ................................ .......................... 87 8.2.4 automatic fcs check ................................ ................................ ................................ . 87 8.2.5 register description ................................ ................................ ................................ .... 87 8.3 re ceived signal strength indicator (rssi) ................................ .......................... 89 8.3.1 overview ................................ ................................ ................................ ..................... 89 8.3.2 reading rssi ................................ ................................ ................................ .............. 89 8.3.3 data interpretation ................................ ................................ ................................ ....... 89 8.3.4 register description ................................ ................................ ................................ .... 90 8.4 energy detection (ed) ................................ ................................ ......................... 91 8.4.1 overview ................................ ................................ ................................ ..................... 91 8.4.2 measurement description ................................ ................................ ............................ 91 8.4.3 data interpretation ................................ ................................ ................................ ....... 92 8.4.4 interrupt handling ................................ ................................ ................................ ........ 92 8.4.5 register description ................................ ................................ ................................ .... 93 8.5 clear channel assessment (cca) ................................ ................................ ....... 94 8.5.1 overview ................................ ................................ ................................ ..................... 94 8.5.2 configuration and request ................................ ................................ .......................... 94 8.5.3 data interpretation ................................ ................................ ................................ ....... 95 8.5.4 interrupt handling ................................ ................................ ................................ ........ 95 8.5.5 measurement time ................................ ................................ ................................ ..... 95 8.5.6 register description ................................ ................................ ................................ .... 96 8.6 li nk quality indication (lqi) ................................ ................................ ................. 99 8.6.1 overview ................................ ................................ ................................ ..................... 99 8.6.2 obtaining the lqi value ................................ ................................ ............................ 100 8.6.3 data interpretation ................................ ................................ ................................ ..... 100 9 module description ................................ ................................ ......... 101 9.1 rece iver (rx) ................................ ................................ ................................ ..... 101 9.1.1 overview ................................ ................................ ................................ ................... 101 9.1.2 frame receive procedure ................................ ................................ ......................... 101 9.1.3 configuration ................................ ................................ ................................ ............. 101 9.1.4 register description ................................ ................................ ................................ .. 102 9.2 transmitter (tx) ................................ ................................ ................................ . 104 9.2.1 overview ................................ ................................ ................................ ................... 104 9.2.2 frame transmit procedure ................................ ................................ ........................ 104 9.2.3 configuration ................................ ................................ ................................ ............. 104
193 8351b C C AT86RF233 9.2.4 tx power ramping ................................ ................................ ................................ ... 105 9.2.5 register description ................................ ................................ ................................ .. 105 9.3 frame buffer ................................ ................................ ................................ ....... 107 9.3.1 data management ................................ ................................ ................................ ..... 107 9.3.2 user accessible frame content ................................ ................................ ................ 108 9.3.3 interrupt handling ................................ ................................ ................................ ...... 108 9.4 voltage regulators (avreg, dvreg) ................................ .............................. 110 9.4.1 overview ................................ ................................ ................................ ................... 110 9.4.2 configurat ion ................................ ................................ ................................ ............. 110 9.4.3 data interpretation ................................ ................................ ................................ ..... 110 9.4.4 register description ................................ ................................ ................................ .. 111 9.5 battery monitor (batmon) ................................ ................................ ................ 113 9.5.1 overview ................................ ................................ ................................ ................... 113 9.5.2 configurat ion ................................ ................................ ................................ ............. 113 9.5.3 data interpretation ................................ ................................ ................................ ..... 113 9.5.4 interrupt handling ................................ ................................ ................................ ...... 114 9.5.5 register description ................................ ................................ ................................ .. 114 9.6 crystal oscillator (xosc) ................................ ................................ ................... 116 9.6.1 overview ................................ ................................ ................................ ................... 116 9.6.2 integrated oscillator setup ................................ ................................ ........................ 116 9.6.3 external reference frequency setup ................................ ................................ ....... 117 9.6.4 master clock signal output (clkm) ................................ ................................ .......... 117 9.6.5 register description ................................ ................................ ................................ .. 118 9.7 frequency synthesizer (pll) ................................ ................................ ............. 121 9.7.1 overview ................................ ................................ ................................ ................... 121 9.7.2 rf channel selection ................................ ................................ ................................ 121 9.7. 3 pll settling time and frequency agility ................................ ................................ ... 122 9.7.4 calibration loops ................................ ................................ ................................ ...... 122 9.7.5 interrupt handling ................................ ................................ ................................ ...... 123 9.7.6 register description ................................ ................................ ................................ .. 123 9.8 automatic filter tuning (ftn) ................................ ................................ ............ 127 9.8.1 overview ................................ ................................ ................................ ................... 127 9.8.2 register description ................................ ................................ ................................ .. 127 10 radio transceiver usage ................................ ............................. 128 10.1 frame receive procedure ................................ ................................ ............... 128 10 .2 frame transmit procedure ................................ ................................ .............. 129 11 AT86RF233 extended feature set ................................ ............... 130 11.1 security module (aes) ................................ ................................ ..................... 130 11.1.1 overview ................................ ................................ ................................ ................. 130 11.1.2 security module preparation ................................ ................................ ................... 130 11.1.3 security key setup ................................ ................................ ................................ .. 131 11.1.4 security operation modes ................................ ................................ ....................... 131 11.1.5 data transfer C fast sram access ................................ ................................ ........ 134 11.1.6 start of security operation and status ................................ ................................ .... 135 11.1.7 sram register summary ................................ ................................ ....................... 135 11.1.8 register description ................................ ................................ ................................ 135 11.2 random number generator ................................ ................................ ............. 138 11.2.1 overview ................................ ................................ ................................ ................. 138
194 8351b C C AT86RF233 11.2.2 register description ................................ ................................ ................................ 138 11.3 high data rate modes ................................ ................................ ..................... 139 11.3.1 overview ................................ ................................ ................................ ................. 139 11.3.2 high data rate packet structure ................................ ................................ ............ 140 11.3.3 high data rate frame buffer access ................................ ................................ ..... 141 11.3.4 high data rate energy detection ................................ ................................ ........... 141 11.3.5 high data rate mode options ................................ ................................ ................. 141 11.3.6 register description ................................ ................................ ................................ 143 11.4 antenna diversity ................................ ................................ ............................. 146 11.4.1 o verview ................................ ................................ ................................ ................. 146 11.4.2 antenna diversity application example ................................ ................................ ... 146 11.4.3 antenna diversity sensitivity control ................................ ................................ ....... 147 11.4.4 register description ................................ ................................ ................................ 148 11.5 rx/tx indicator ................................ ................................ ................................ 151 11.5.1 ove rview ................................ ................................ ................................ ................. 151 11.5.2 external rf - front end control ................................ ................................ ................ 151 11.5.3 register description ................................ ................................ ................................ 152 11.6 rx and tx frame time stamping (tx_aret) ................................ ............... 153 11.6.1 overview ................................ ................................ ................................ ................. 153 11.6.2 register description ................................ ................................ ................................ 153 11.7 frame buffer empty indicator ................................ ................................ .......... 155 11.7.1 overview ................................ ................................ ................................ ................. 155 11.7.2 register description ................................ ................................ ................................ 156 11.8 dynamic frame buffer protection ................................ ................................ .... 157 11.8.1 overview ................................ ................................ ................................ ................. 157 11.8.2 register description ................................ ................................ ................................ 157 11.9 alternate start - of - frame delimiter ................................ ................................ .. 158 11.9.1 overview ................................ ................................ ................................ ................. 158 11.9.2 register description ................................ ................................ ................................ 158 11.10 reduced power consumption mode (rpc) ................................ .................. 159 11.10.1 overview ................................ ................................ ................................ ............... 159 11.10.2 rpc methods and elements ................................ ................................ ................. 159 11.10.3 register summary ................................ ................................ ................................ . 162 12 electrical characteristics ................................ ............................. 164 12.1 absolute maximum ratings ................................ ................................ .............. 164 12.2 recommended operating range ................................ ................................ ..... 164 12.3 digital pin characteristics ................................ ................................ ................ 165 12.4 digital interface timing characteristics ................................ ............................ 165 12.5 general rf specifications ................................ ................................ ................ 166 12.6 transmitter characteristics ................................ ................................ .............. 167 12.7 receiver characteristics ................................ ................................ .................. 167 12.8 current consumption specifications ................................ ................................ 168 12.9 crystal parameter requirements ................................ ................................ ..... 169 13 typical characteristics ................................ ................................ . 170
1 95 8351b C C AT86RF233 13.1 active supply current ................................ ................................ ....................... 170 13.1.1 p_on and trx_off states ................................ ................................ .................... 170 13.1.2 pll_on state ................................ ................................ ................................ .......... 171 13.1.3 rx_on state ................................ ................................ ................................ ........... 172 13.1.4 tx_busy state ................................ ................................ ................................ ....... 173 13.1.5 sle ep ................................ ................................ ................................ ..................... 175 13.1.6 deep_sleep ................................ ................................ ................................ ......... 175 13.2 state transition timing ................................ ................................ .................... 176 14 register reference ................................ ................................ ....... 178 15 abbreviations ................................ ................................ ................ 181 16 ordering information ................................ ................................ .... 183 17 soldering information ................................ ................................ ... 183 18 package thermal properties ................................ ........................ 183 19 package drawing C 32qn2 ................................ ........................... 184 appendix a - continuous transmission test mode ....................... 185 a.1 - overview ................................ ................................ ................................ .......... 185 a.2 - configuration ................................ ................................ ................................ .... 185 a.3 C regist er description ................................ ................................ ........................ 187 appendix b - errata ................................ ................................ ........... 188 AT86RF233 rev. a ................................ ................................ ................................ .. 188 references ................................ ................................ .......................... 189 data sheet revision history ................................ ............................. 190 rev. 8351b C mcu wireless C 06/12 ................................ ................................ ........... 190 rev. 8351a C mcu wireless C 02/12 ................................ ................................ ........... 190 table of contents ................................ ................................ ............... 191
196 8351b C C AT86RF233 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441 - 0311 fax: (+1)(408) 487 - 2600 www.atmel.com atmel asia limited unit 01 - 5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245 - 6100 fax: (+852) 2722 - 1369 atmel munich gmbh business campus parkring 4 d - 85748 garching b. munich germany tel: (+49) 89 - 31970 - 0 fax: (+49) 89 - 3194621 atmel japan g. k. 16f shin - osaki kangyo bldg. 1 - 6 - 4 osaki, shinagawa - ku tokyo 141 - 0032 japan tel: (+81)(3) 6417 - 0030 fax: (+81)(3) 6417 - 0370 ? 201 2 atmel corporation. all rights reserved . atmel ? , atmel logo and combinations thereof, avr ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel o r otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel p roducts. except as set forth in the atmel terms and condi tions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or non - infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or inciden tal damages (including, without limitation, damages for lo ss and profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the acc uracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herei n. unless speci fically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products ar e not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

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